Memory controllers, memory systems, solid state drives and methods for processing a number of commands

• US 8,751,700 B2
• Filed: 03/12/2013
• Issued: 06/10/2014
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Liao, Yu-Song, Yang, Jui-Yao, Nemazie, Siamack
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US13/796,851
• Publication Number:
  US 20130268701A1
• Time in Patent Office: 455 Days
• Field of Search: None
• US Class Current: 710/22
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Claims

1. A memory system, comprising:

a plurality of memory devices; and

a controller having a front end direct memory access module (DMA) and a number of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA;

the front end DMA being configured to process a payload associated with a single host command communicated by the host, wherein respective portions of the payload are associated with corresponding multiple back end commands that are being substantially simultaneously executed across the number of back end channels,

wherein each back end channel corresponds to a different one of the plurality of memory devices.

2. The memory system of claim 1, wherein the single host command is a write command, and the front end DMA is configured to distribute the payload associated with the single host command amongst more than one of the number of back end channels corresponding to the multiple back end commands.

3. The memory system of claim 1, wherein the single host command is a read command, and the front end DMA is configured to assemble a payload associated with the single host command from amongst more than one of the number of back end channels corresponding to the multiple back end commands.

4. The memory system of claim 1, wherein the front end DMA is configured to determine a logical block address and sector count for each respective portion of the payload associated with each of the multiple back end commands, wherein each of the multiple back end commands mimic the host command but with a modified respective logical block address and sector count corresponding to a respective one of the number of back end channels.

5. The memory system of claim 1, wherein the front end DMA is configured to communicate portions of the payload associated with the multiple back end commands to a host in an order different than an order in which the host command would have produced the payload if it had been executed by a single back end channel.

6. The memory system of claim 5, wherein the front end DMA is configured to communicate portions of the payload associated with the multiple back end commands in an order in which the portions are received from the plurality of back end channels.

7. The memory system of claim 1, wherein the front end DMA is configured to communicate indicators of command completion status to the host in an order different than an order in which host commands are communicated by the host.

8. The memory system of claim 7, wherein the front end DMA is configured to communicate an indicator of command completion status to the host in an order in which back end commands are completed by the number of back end channels.

9. The memory system of claim 1, wherein each of the portions corresponds to a particular back end channel, and wherein the front end DMA is configured to communicate each of the portions individually to the host separate from the other portions.

10. The memory system of claim 9, wherein the front end DMA is configured to communicate one of the portions to the host upon receipt of the respective portion from one of the number of back end channels, and without assembling the portions into a complete payload associated with the single host command.

11. The memory system of claim 10, wherein the single host command is a read command and each of the portions is associated with a different back end channel.

12. The memory system of claim 10, wherein the front end DMA is configured to communicate each of the portions to the host as one of the number of back end channels completes processing the portion associated therewith.

13. The memory system of claim 1, wherein the single host command is a write command received at the front end DMA as part of a first order of host commands, the host commands being completed in a second order, and the front end DMA is configured to communicate an indicator of a command completion status of the single host command to the host according to the second order.

14. A memory system, comprising:

a number of memory devices; and

a controller having;

a front end direct memory access module (DMA); and

a plurality of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA, each back end channel corresponding to a different memory device, the front end DMA being configured to;

generate a number of back end commands at least in response to a number of the host commands in a command queue, wherein the number of back end commands is different than the number of the host commands, and

distribute the number of back end commands to the plurality of back end channels, wherein the number of back end commands is at least equal to a quantity of the plurality of back end channels.

15. The memory system of claim 14, wherein the number of back end commands is fewer than the number of the host commands.

16. The memory system of claim 14, wherein the number of back end commands is greater than the number of the host commands.

17. The memory system of claim 14, wherein the front end DMA is configured to:

generate a respective back end command corresponding to each of the plurality of back end channels in response to a single host command, and

distribute the respective back end command to its corresponding back end channel, such that the back end commands are processed substantially in parallel.

18. A memory system, comprising:

a number of memory devices; and

a controller having;

a front end direct memory access module (DMA); and

a number of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA, the front end DMA being configured to;

determine a net read from the number of memory devices to be accomplished a number of read commands; and

modify one or more of the number of read commands such that fewer commands are sent to accomplish the same net read from the number of memory devices in order to economize distribution of the number of read commands among the plurality of back end channels,

wherein each of the number of back end channels corresponds to a different one of the number of memory devices.

19. The memory system of claim 18, wherein the front end DMA is configured to:

determine a net change to memory to be accomplished by a number of write commands; and

modify one or more of the number of write commands such that fewer commands are sent to accomplish the same net change to the number of memory devices in order to economize distribution of the number of write commands among the plurality of back end channels.

20. The memory system of claim 18, wherein the front end DMA is configured to:

determine a net change to memory to be accomplished by a number of write commands; and

modify one or more of the number of write commands in order to optimize distribution of the number of write commands among the plurality of back end channels.