Memory super block allocation

• US 8,751,731 B2
• Filed: 08/06/2012
• Issued: 06/10/2014
• Est. Priority Date: 03/04/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Chen, Alan, Nemazie, Siamack, McNamara, Dale P.
• Primary Examiner(s): Sadler, Nathan
• Application Number:
  US13/567,680
• Publication Number:
  US 20120303931A1
• Time in Patent Office: 673 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

Claims

1. A memory controller, comprising:

control circuitry coupled to one or more memory devices having multiple groups of planes associated therewith, each group including at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to;

receive a first unassigned logical block address (LBA) associated with a write operation;

determine a particular free super block within a selected one of the multiple groups to receive data associated with the write operation;

receive a different unassigned LBA associated with a subsequent write operation;

determine a particular free super block within a selected one of the multiple groups to receive data associated with the subsequent write operation;

track, for each of the multiple groups, a number of free super blocks available in each group;

determine which of the super blocks have stale data;

determine when the super blocks having stale data are to be erased; and

for each of the multiple groups, prevent the super blocks having stale data from being erased until the group does not include any free super blocks.

2. The memory controller of claim 1, wherein the selected one of the multiple groups associated with the subsequent write operation is different from the selected one of the multiple groups associated with the write operation.

3. The memory controller of claim 1, wherein the control circuitry is configured to select the one of the multiple groups to receive data associated with the write operation based, at least partially, on the number of free super blocks available in each of the multiple groups.

4. The memory controller of claim 1, wherein the control circuitry is configured to select the one of the multiple groups to receive data associated with the write operation based, at least partially, on a ratio of free super blocks to used super blocks for each of the multiple groups.

5. The memory controller of claim 1, wherein the control circuitry is configured to add erased super blocks to the number of free super blocks available in each group at particular times and on a group by group basis.

6. A system, comprising

a controller;

and

a number of memory devices coupled to the controller, the number of memory devices having multiple groups of planes associated therewith, each group including at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes;

wherein the controller is configured to control;

receiving a first unassigned logical block address (LBA) associated with a write operation;

determining a particular free super block within a selected one of the multiple groups to receive data associated with the write operation;

assigning the first unassigned LBA to the selected one of the multiple groups such that data associated with all subsequent write operations corresponding to the previously unassigned first LBA is written to a free super block within the respective assigned group;

tracking, for each of the multiple groups, a number of free super blocks available in each group;

determining which of the super blocks have stale data;

determining when the super blocks having stale data are to be erased; and

for each of the multiple groups, preventing the super blocks having stale data from being erased until the respective group does not include any free super blocks.

7. The system of claim 6, wherein the controller is configured to control selecting the one of the multiple groups to receive data associated with the write operation based, at least partially, on a ratio of free super blocks to used super blocks for each of the multiple groups.

8. The system of claim 6, wherein the controller is configured to:

receive a different unassigned LBA associated with a subsequent write operation; and

determine a particular free super block within a selected one of the multiple groups to receive data associated with the subsequent write operation.

9. The system of claim 8, wherein the controller is configured to select the one of the multiple groups to receive data associated with the subsequent write operation on a round-robin basis.

10. The system of claim 8, wherein the selected one of the multiple groups associated with the subsequent write operation is different from the selected one of the multiple groups associated with the write operation.

11. The system of claim 6, wherein the controller is configured to add erased super blocks to the number of free super blocks available in each group at particular times and on a group by group basis.

12. A method for block selection, the method comprising:

receiving a first unassigned logical block address (LBA) in association with a first write operation;

writing data corresponding to the first write operation to a selected free super block within a selected group of multiple groups of planes;

assigning the first unassigned LBA to the selected group such that data associated with a number of subsequent write operations corresponding to the first unassigned LBA is written to a free super block within the assigned selected group;

receiving a second unassigned LBA in association with a subsequent write operation; and

writing data corresponding to the subsequent write operation to a selected free super block within a selected one of the multiple groups;

removing the free super block written to in association with the first write operation from a list of available free super blocks associated with the respective selected group after the first write operation;

removing the super block written to in association with the second write operation from a list of available free super blocks associated with the respective selected group after the subsequent write operation;

preventing a respective one of the removed super blocks from being returned to a respective one of the lists until each of the super blocks of the respective one of the groups has been written to at least once; and

for each of the multiple groups of planes, preventing super blocks having stale data from being erased until the respective group does not include any free super blocks.

13. The method of claim 12, including selecting the selected group associated with the first write operation based, at least partially, on a ratio of free super blocks to used super blocks in the respective selected group as compared to a ratio of free super blocks to used super blocks in each of the other groups.

14. The method of claim 12, wherein selecting the selected one of the multiple groups associated with the subsequent write operation includes selecting a group different from the selected one of the multiple groups associated with the first write operation.

15. The method of claim 12, including, for each group:

tracking a number of free super blocks in the group;

removing a super block from a list of free super blocks subsequent to the super block being written to; and

adding the super block to the list of free super blocks subsequent to the super block being erased.

16. The method of claim 12, wherein each of the multiple groups of planes is a collection of at least two planes with each of the super blocks being a respective collection of one physical block from each of the at least two planes.

17. The method of claim 12, including selecting the one of the multiple groups corresponding to the subsequent write operation on a round-robin basis.