Mass storage controller volatile memory containing metadata related to flash memory storage

• US 8,751,755 B2
• Filed: 04/08/2008
• Issued: 06/10/2014
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Prins, Douglas A., Olbrich, Aaron K.
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/082,206
• Publication Number:
  US 20090172259A1
• Time in Patent Office: 2,254 Days
• Field of Search: 711/5, 711/140, 711/147, 711/169, 710/317
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata.

Claims

1. An external memory coupled to a mass storage controller, wherein the mass storage controller is coupled to a plurality of groups of flash memory devices, the external memory comprising:

a portion for a data buffer for holding data received by the mass storage controller from one or more hosts, and for holding data received by the mass storage controller from the plurality of groups of flash memory devices coupled to the mass storage controller, each group of flash memory devices comprising a plurality of banks, each bank comprising a plurality of blocks, each block comprising a minimum size erase unit of flash memory and further comprising a plurality of superpages, each superpage comprising a plurality of flash pages, wherein each group of flash memory devices further includes a plurality of superblocks, wherein each superblock includes a corresponding block from each bank of the plurality of banks in the group of flash memory devices;

a portion for a first table including a series of physical addresses in the plurality of groups of flash memory devices, the series of physical addresses arranged in an order reflecting a logical addressing system used by the one or more hosts, the first table including one physical flash memory address for every n addresses from the logical addressing system, n being larger than one and representing the number of logical addresses assignable to each superpage, and further including a field to store a count for the number of times each of the physical flash memory addresses has been accessed;

a portion for a plurality of second tables, the plurality of second tables comprising a separate second table for each group of flash memory devices, each second table indicating,

for each superpage in a respective group of flash memory devices, whether the superpage contains valid data, and

for each superblock in the respective group of flash memory devices, a count for the number of superpages in the superblock which store invalid data and a count for the number of times the superblock has been erased; and

an interface to the mass storage controller, wherein the mass storage controller is configured to generate and store aggregated data in the external memory, the aggregated data including data stored in the first table and the plurality of second tables in the external memory.

2. The external memory as in claim 1, further including:

a portion for a plurality of firmware overlays, related to a plurality of processors, the firmware overlays including program code to be loaded by and used by the processors.

3. The volatile external memory as in claim 1, further including:

a portion for a third table holding Small Computer Systems Interface (SCSI) tag information, the third table including a plurality of indicators, each indicator indicating whether one or more SCSI tags is currently active in the storage controller.

4. The external memory as in claim 3, wherein:

the third table further includes information identifying an initiator for each currently active SCSI tag.

5. The external memory as in claim 1, wherein:

n is a number ranging from approximately twelve (12) to approximately sixteen (16).

6. The external memory as in claim 5, wherein:

each first table physical flash memory address represents a location on more than one flash memory die.

7. The external memory as in claim 6, further including:

a portion for a plurality of third tables, each containing information relating to an area of flash memory device that is currently open for writing, the information including a time stamp and an indication regarding whether a subset of the area is defective.

8. The external memory as in claim 7, wherein:

each third table further includes an erase count for the area or for a subset of the area and information associating logical addresses with physical addresses that are within the area.

9. The external memory as in claim 8, wherein:

the mass storage controller includes a plurality of flash ports, and

each third table is associated with each flash port.

10. A method of operating a system, the system including a mass storage controller, an external memory coupled to the mass storage controller, the mass storage controller coupled to a plurality of groups of flash memory devices, the method comprising:

storing, in a data buffer in the external memory, a first data received by the mass storage controller from one or more hosts, and a second data received by the mass storage controller from the plurality of groups of flash memory devices coupled to the mass storage controller, each group of flash memory devices comprising a plurality of banks, each bank comprising a plurality of blocks, each block comprising a minimum size erase unit of flash memory and further comprising a plurality of superpages, each superpage comprising a plurality of flash pages, wherein each group of flash memory devices further includes a plurality of superblocks, wherein each superblock includes a corresponding block from each bank of the plurality of banks in the group of flash memory devices;

translating, using a first table in the external memory, logical addresses received from the one or more hosts into physical addresses in the plurality of groups of flash memory devices, wherein n logical addresses are assigned to a single physical address, n being larger than one and representing the number of logical addresses assignable to each superpage, wherein the first table includes a series of physical addresses in the plurality of groups of flash memory devices, the series of physical addresses arranged in an order reflecting a logical addressing system used by the one or more hosts, the first table including one physical flash memory address for every n addresses from the logical addressing system and further including a field to store a count for the number of times each of the physical flash memory addresses has been accessed; and

storing, in a plurality of second tables in the external memory, the plurality of second tables comprising a separate second table for each group of flash memory devices, data indicating,

for each superpage in a respective group of flash memory devices, whether the superpage contains valid data, and

for each superblock in the respective group of flash memory devices, a count for the number of superpages in the superblock which store invalid data and a count for the number of times the superblock has been erased.

11. The method of claim 10, wherein the external memory further includes:

a portion for a plurality of firmware overlays, related to a plurality of processors, the firmware overlays including program code to be loaded by and used by the processors.

12. The method of claim 10, wherein the external memory further includes:

a portion for a third table holding Small Computer Systems Interface (SCSI) tag information, the third table including a plurality of indicators, each indicator indicating whether one or more SCSI tags is currently active in the storage controller.

13. The method of claim 12, wherein the third table further includes information identifying an initiator for each currently active SCSI tag.

14. The method of claim 10, wherein n is a number ranging from approximately twelve (12) to approximately sixteen (16).

15. The method of claim 14, wherein each first table physical flash memory address represents a location on more than one flash memory die.

16. The method of claim 15, wherein the external memory further includes:

a portion for a plurality of third tables, each containing information relating to an area of flash memory device that is currently open for writing, the information including a time stamp and an indication regarding whether a subset of the area is defective.

17. The method of claim 16, wherein:

each third table further includes an erase count for the area or for a subset of the area and information associating logical addresses with physical addresses that are within the area.

18. The method of claim 17, wherein:

the mass storage controller includes a plurality of flash ports, and

each third table is associated with each flash port.

19. A system including a mass storage controller, an external memory coupled to the mass storage controller, the mass storage controller coupled to a plurality of groups of flash memory devices, the system comprising:

one or more ports for coupling to one or more hosts;

the external memory coupled to the mass storage controller; and

the mass storage controller coupled to the plurality of groups of flash memory devices, each group of flash memory devices comprising a plurality of banks, each bank comprising a plurality of blocks, each block comprising a minimum size erase unit of flash memory and further comprising a plurality of superpages, each superpage comprising a plurality of flash pages, wherein each group of flash memory devices further includes a plurality of superblocks, wherein each superblock includes a corresponding block from each bank of the plurality of banks in the group of flash memory devices, the mass storage controller configured to generate and store aggregated data in the external memory;

the external memory including;

an interface to the mass storage controller;

a portion for a data buffer for holding data received by the mass storage controller from the one or more hosts, and for holding data received by the mass storage controller from the plurality of groups of flash memory devices coupled to the mass storage controller;

a portion for a first table including a series of physical addresses in the plurality of groups of flash memory devices, the series of physical addresses arranged in an order reflecting a logical addressing system used by the one or more hosts, the first table including one physical flash memory address for every n addresses from the logical addressing system, n being larger than one and representing the number of logical addresses assignable to each superpage, and further including a field to store a count for the number of times each of the physical flash memory addresses has been accessed; and

a portion for a plurality of second tables, the plurality of second tables comprising a separate second table for each group of flash memory devices, each second table indicating,

for each superpage in a respective group of flash memory devices, whether the superpage contains valid data, and

for each superblock in the respective group of flash memory devices, a count for the number of superpages in the superblock which store invalid data and a count for the number of times the superblock has been erased.

20. The system of claim 19, wherein the external memory further includes:

a portion for a plurality of firmware overlays, related to a plurality of processors, the firmware overlays including program code to be loaded by and used by the processors.

21. The system of claim 19, wherein the external memory further includes:

a portion for a third table holding Small Computer Systems Interface (SCSI) tag information, the third table including a plurality of indicators, each indicator indicating whether one or more SCSI tags is currently active in the storage controller.

22. The system of claim 21, wherein the third table further includes information identifying an initiator for each currently active SCSI tag.

23. The system of claim 19, wherein n is a number ranging from approximately twelve (12) to approximately sixteen (16).

24. The system of claim 23, wherein each first table physical flash memory address represents a location on more than one flash memory die.

25. The system of claim 24, wherein the external memory further includes:

a portion for a plurality of third tables, each containing information relating to an area of flash memory device that is currently open for writing, the information including a time stamp and an indication regarding whether a subset of the area is defective.

26. The system of claim 25, wherein:

each third table further includes an erase count for the area or for a subset of the area and information associating logical addresses with physical addresses that are within the area.

27. The system of claim 26, wherein:

the mass storage controller includes a plurality of flash ports, and

each third table is associated with each flash port.