Compiling method and processor using the same

• US 8,752,031 B2
• Filed: 12/01/2008
• Issued: 06/10/2014
• Est. Priority Date: 02/27/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Taisong, Kim, Hong-Seok, Baek, Chang-Woo
• Primary Examiner(s): Dao, Thuy
• Assistant Examiner(s): Smith, Cheneca
• Application Number:
  US12/325,361
• Publication Number:
  US 20090217249A1
• Time in Patent Office: 2,017 Days
• Field of Search: None
• US Class Current: 717/135
• CPC Class Codes: G06F 8/41 Compilation

Abstract

A compiling method and a processor using the same are provided. The compiling method includes simulating a first program code which includes at least one first operation command to generate a first operation result, compiling the first program code to generate a second program code which includes at least one second operation command, simulating the second program code to generate a second operation result, and comparing the first operation result with the second operation result to verify whether the second program code is valid.

Claims

1. A compiling method, the method comprising:

simulating program code which includes at least one first operation command to generate a first operation result;

translating the program code into machine code of a processor that comprises at least one second operation command;

simulating the machine code to generate a second operation result; and

comparing the first operation result with the second operation result to verify whether the machine code is valid, wherein;

the translating of the program code comprises register-allocating the program code, and

the simulating of the program code comprises simulating the program code by referring to stack information of the machine code, which is generated after the program code is register-allocated.

2. The method of claim 1, wherein:

the translating of the program code further comprises assigning an operation identifier to each of the at least one first operation command, and

the comparing of the first operation result with the second operation result comprises comparing an operation result of each of the at least one first operation command with an operation result of one of the at least one second operation command which corresponds to the operation identifier assigned to the first operation command.

3. The method of claim 1, wherein the comparing of the first operation result with the second operation result does not verify an operation result of the at least one second operation command having no corresponding operation identifier from among operation identifiers assigned to the at least one first operation command.

4. The method of claim 1, wherein the comparing of the first operation result with the second operation result does not verify an operation result of the at least one first operation command having no second operation command which corresponds to operation identifiers assigned to the at least one first operation command.

5. The method of claim 1, wherein the translating of the program code comprises scheduling the program code based on parallelism of a processor where the program code is executed.

6. The method of claim 1, wherein the translating of the program code further comprises register-allocating the program code so that a number of registers which are simultaneously activated while the program code is executed does not surpass a number of registers supported by hardware.

7. A non-transitory computer-readable storage medium storing a program to implement a compiling method, the program comprising instructions to cause a computer to:

simulate program code which includes at least one first operation command to generate a first operation result;

translate the program code into machine code of a processor that comprises at least one second operation command;

simulate the machine code to generate a second operation result; and

compare the first operation result with the second operation result to verify whether the machine code is valid, wherein;

the translating of the program code comprises register-allocating the program code, and

the simulating of the program code comprises simulating the program code by referring to stack information of the machine code, which is generated after the program code is register-allocated.

8. A processor comprising:

a code transformer configured to translate program code which includes at least one first operation command into machine code of a computer comprising at least one second operation command;

a first simulator configured to simulate the program code to generate a first operation result; and

a second simulator configured to simulate the machine code to generate a second operation result, wherein;

the processor verifies whether the machine code is valid by comparing the first operation result and the second operation result,

the code transformer register-allocates the program code and transmits stack information of the machine code, which is generated after the program code is register-allocated, and

the first simulator simulates the program code by referring to the stack information.

9. The processor of claim 8, wherein:

the code transformer assigns an operation identifier to each of the at least one first operation command, and

the processor compares an operation result of each of the at least one first operation command with an operation result of one of the at least one second operation command which corresponds to the operation identifier assigned to the first operation command.

10. The processor of claim 8, wherein the code transformer register-allocates the program code so that a number of registers which are simultaneously activated while the program code is executed does not surpass a number of registers supported by hardware.

11. The processor of claim 8, wherein the processor is a reconfigurable processor having a plurality of functional units that are configured to be used in parallel according to operation commands to be executed.