Method for fabricating novel semiconductor and optoelectronic devices

• US 8,753,913 B2
• Filed: 03/16/2012
• Issued: 06/17/2014
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US13/422,049
• Publication Number:
  US 20120231572A1
• Time in Patent Office: 823 Days
• Field of Search: 438/39, 438/46, 438/47, 438/93, 438/94
• US Class Current: 438/59
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14605 Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/34 containing only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors.

Claims

1. A method for fabricating an integrated device, comprising:

overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the said first and second crystalline layers is an image sensor layer; and

performing an atomic species implantation to transfer at least one of the said first and second crystalline layers;

wherein at least one of the said first and second crystalline layers comprises single crystal transistors.

2. A method for fabricating an integrated device according to claim 1, wherein

said image sensor layer and said single crystal transistors are aligned to each other, and wherein said aligned has less than 1 micron alignment error.

3. A method for fabricating an integrated device according to claim 1, wherein

said image sensor layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer is sensitive to a different spectrum than said second image sensor layer.

4. A method for fabricating an integrated device according to claim 1, wherein

said image sensor layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer has at least an order of magnitude difference in light sensitivity than said second image sensor layer.

5. A method for fabricating an integrated device according to claim 1, wherein

said image sensor layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

the construction process of at least one of said two crystalline layers comprises atomic species implantation.

6. A method for fabricating an integrated device according to claim 1, wherein

said second crystalline layer is an image sensor layer, and wherein

said image sensor layer is processed after said transferred.

7. A method for fabricating an integrated device according to claim 1, wherein

said single crystal transistors form a plurality of pixel control circuits.

8. A method for fabricating an integrated device, comprising:

processing a first mono-crystal layer to comprise a plurality of image sensor pixels and alignment marks, and then

overlaying oxide on top of said first mono-crystal layer, and then

transferring a second mono-crystal layer on said oxide, and then

processing said second mono-crystal layer to comprise a plurality of single crystal transistors aligned to said alignment marks, wherein said aligned has less than 1 micron alignment error.

9. A method for fabricating an integrated device according to claim 8, wherein

said transferring comprises atomic species implantation.

10. A method for fabricating an integrated device according to claim 8, wherein

said image sensor pixels and said single crystal transistors are aligned to each other.

11. A method for fabricating an integrated device according to claim 8, wherein

said first mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer is sensitive to a different spectrum than said second image sensor layer.

12. A method for fabricating an integrated device according to claim 8, wherein

said first mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer has at least an order of magnitude difference in light sensitivity than said second image sensor layer.

13. A method for fabricating an integrated device according to claim 8, wherein

said first mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

the construction process of at least one of said two crystalline layers comprises atomic species implantation.

14. A method for fabricating an integrated device according to claim 8, wherein

said first mono-crystal layer comprises a polarizer.

15. A method for fabricating an integrated device according to claim 8, wherein

said single crystal transistors form a plurality of pixel control circuits.

16. A method for fabricating an integrated device, comprising:

processing a first mono-crystal layer to comprise a plurality of single crystal transistors and alignment marks, and then

overlaying oxide on top of said first mono-crystal layer, and then

transferring a second mono-crystal layer on said oxide, and then

processing said second mono-crystal layer to comprise a plurality of image sensor pixels aligned to said alignment marks, and

wherein said aligned has less than 1 micron alignment error.

17. A method for fabricating an integrated device according to claim 16, wherein

said transferring comprises atomic species implantation.

18. A method for fabricating an integrated device according to claim 16, wherein

said image sensor pixels and said single crystal transistors are aligned to each other.

19. A method for fabricating an integrated device according to claim 16, wherein

said second mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer is sensitive to a different spectrum than said second image sensor layer.

20. A method for fabricating an integrated device according to claim 16, wherein

said second mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

said first image sensor layer has at least an order of magnitude difference in light sensitivity than said second image sensor layer.

21. A method for fabricating an integrated device according to claim 16, wherein

said second mono-crystal layer comprises two crystalline layers, wherein;

said two crystalline layers comprise a first image sensor layer and a second image sensor layer, and wherein;

the construction process of at least one of said two crystalline layers comprises atomic species implantation.

22. A method for fabricating an integrated device according to claim 16, wherein

said second mono-crystal layer comprises a polarizer.

23. A method for fabricating an integrated device according to claim 16, wherein

said single crystal transistors form a plurality of pixel control circuits.