Method of fabricating photoconductor-on-active pixel device

• US 8,753,917 B2
• Filed: 12/14/2010
• Issued: 06/17/2014
• Est. Priority Date: 12/14/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Leidy, Robert K., Rassel, Richard J.
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US12/967,625
• Publication Number:
  US 20120146115A1
• Time in Patent Office: 1,281 Days
• Field of Search: 257/291, 257/292, 257/444, 257/E31.056, 257/E31.057, 257/331.06, 257/E31.084, 257/E31.085, 438/57, 438/98
• US Class Current: 438/98
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type

Abstract

A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.

Claims

1. A method for fabricating a photoconductor-on-active pixel device, the method comprising:

depositing a conductive layer on a first dielectric layer;

depositing a first capping layer on the conductive layer;

removing portions of the conductive layer and the first capping layer to define a first conductive pad portion and a first interconnect portion, and expose portions of the first dielectric layer;

depositing a second dielectric layer on the exposed portions of the first dielectric layer;

selectively etching the second dielectric layer with respect to the first capping layer thereby stopping on the first capping layer such that an upper surface of the second dielectric layer is flush with an upper surface of remaining portions of the first capping layer;

depositing a second capping layer on the first capping layer and the second dielectric layer;

removing portions of the second capping layer to expose portions of the second dielectric layer and removing portions of the second capping layer and first capping layer to expose a portion of the first conductive pad portion; and

forming radiation absorbing layers on the exposed portions of the second dielectric layer, the exposed portion of the first conductive pad portion, and the second capping layer.

2. The method of claim 1, wherein prior to depositing the conductive layer on the first dielectric layer the method includes:

forming a field effect transistor device on a substrate;

forming an interconnect layer over the field effect transistor device, the interconnect layer including a second conductive pad portion and a second interconnect portion disposed in a third dielectric layer; and

forming a first conductive via and a second conductive via in the third dielectric layer, the first conductive via contacting the first conductive pad portion and the second conductive pad portion and the second conductive via contacting the first interconnect portion and the second interconnect portion.

3. The method of claim 1, wherein the forming the radiation absorbing layers includes:

forming an n-type doped layer;

forming an intrinsic layer on the n-type doped layer; and

forming a p-type doped layer on the intrinsic layer.

4. The method of claim 1, wherein the method includes forming a conductive transparent layer over the radiation absorbing layers.

5. The method of claim 3, wherein the radiation absorbing layers are formed by an epitaxial silicon growth process.

6. The method of claim 1, wherein the conductive layer includes aluminum.

7. The method of claim 2, wherein the conductive vias include tungsten.

8. The method of claim 2, wherein the second conductive pad portion and the second interconnect portion include copper.

9. The method of claim 1, wherein the first capping layer and the second capping layer include a nitride material.

10. A method for fabricating a photoconductor-on-active pixel device, the method comprising:

depositing a conductive layer on a first dielectric layer and on, and in contact with conductive vias;

depositing a first capping layer on the conductive layer;

removing portions of the conductive layer and the first capping layer to define a first conductive pad portion and a first interconnect portion, and expose portions of the first dielectric layer;

depositing a second dielectric layer on the exposed portions of the first dielectric layer;

selectively etching the second dielectric layer with respect to the first capping layer thereby stopping on the first capping layer such that an upper surface of the second dielectric layer is flush with an upper surface of remaining portions of the first capping layer;

depositing a second capping layer on the first capping layer and the second dielectric layer;

removing portions of the second capping layer to expose portions of the second dielectric layer and removing portions of the second capping layer and first capping layer to expose a portion of the first conductive pad portion; and

forming radiation absorbing layers on the exposed portions of the second dielectric layer, the exposed portion of the first conductive pad portion, and the second capping layer.

11. The method of claim 10, wherein prior to depositing the conductive layer on the first dielectric layer the method includes:

forming a field effect transistor device on a substrate;

forming an interconnect layer over the field effect transistor device, the interconnect layer including a second conductive pad portion and a second interconnect portion disposed in a third dielectric layer; and

forming a first conductive via and a second conductive via in the third dielectric layer, the first conductive via contacting the first conductive pad portion and the second conductive pad portion and the second conductive via contacting the first interconnect portion and the second interconnect portion.

12. The method of claim 10, wherein the forming the radiation absorbing layers includes:

forming an n-type doped layer;

forming an intrinsic layer on the n-type doped layer; and

forming a p-type doped layer on the intrinsic layer.

13. The method of claim 10, wherein the method includes forming a conductive transparent layer over the radiation absorbing layers.

14. The method of claim 12, wherein the radiation absorbing layers are formed by an epitaxial silicon growth process.

15. The method of claim 10, wherein the conductive layer includes aluminum.

16. The method of claim 11, wherein the conductive vias include tungsten.

17. The method of claim 11, wherein the second conductive pad portion and the second interconnect portion include copper.

18. The method of claim 10, wherein the first capping layer and the second capping layer include a nitride material.