High frequency switching MOSFETs with low output capacitance using a depletable P-shield

• US 8,753,935 B1
• Filed: 12/21/2012
• Issued: 06/17/2014
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Yilmaz, Hamza, Lui, Sik, Ng, Daniel
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US13/724,093
• Publication Number:
  US 20140175540A1
• Time in Patent Office: 543 Days
• Field of Search: 438/270, 438/272, 257/334, 257/E29.26, 257/E29.263
• US Class Current: 438/270
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A Method for forming a MOSFET device comprising:

a) forming a hardmask over a top surface of a semiconductor substrate of a first conductivity type, wherein the hardmask includes first and second insulator layers, wherein the second insulator layer is resistant to a first etching process that etches the first insulator layer, and the first insulator layer is resistant to a second etching process that etches the second insulator layer;

b) etching the semiconductor substrate through openings in the hardmask to form a plurality of trenches in the semiconductor substrate, wherein the trenches comprise an upper portion and a lower portion;

c) lining the upper portion with an upper insulative layer of a first thickness T₁ and lining the lower portion with a lower insulative layer of a second thickness T_z, wherein T₂ is greater than T₁;

d) disposing a conductive material in the trenches to form a plurality of gate electrodes;

e) forming insulative gate caps above the gate electrodes up to at least a level of the second layer of the hardmask, wherein the insulative gate caps are made of a material that is etched by the first etch process and resistant to the second etch process;

f) removing the first layer of the hardmask using the first etch process, leaving the insulative gate caps aligned with the trenches protruding above a level of the second layer of the hardmask;

g) forming a body layer in a top portion of the substrate, wherein the body layer is a second conductivity type that is opposite of the first conductivity type;

h) forming a depletable shield of the second conductivity type in the semiconductor substrate at a depth at least partially below a bottom surface of the trenches, wherein the depletable shield is electrically connected to the body layer;

i) forming an insulative spacer layer over the second layer of the hardmask and the gate caps;

j) forming a conductive or semiconductor spacer layer over the insulative spacer layer, and anisotropically etching the conductive or semiconductor spacer layer and the insulative spacer layer leaving portions of the conductive or semiconductor spacer layer and the insulative spacer layer along the sidewalls of the gate caps as conductive or semiconductor spacers and insulative spacers; and

k) forming openings into the semiconductor substrate for source contacts using the conductive or semiconductor spacers as a self-aligning mask.

2. The method of claim 1, wherein one or more of the depletable shields extend through the substrate to a drain contact of the first conductivity type formed in a bottom portion of the substrate.

3. The method of claim 1, wherein one or more of the depletable shields are formed completely below the bottom surface of the trenches.

4. The method of claim 1, wherein the connection between the depletable shield and the body layer is made in a primary plane of the device.

5. The method of claim 1, wherein the connection between the depletable shield and the body layer is made in a secondary plane of the device, wherein the secondary plane of the device is orthogonal to the primary plane of the device.

6. The method of claim 5, wherein a portion of the depletable shield is disconnected from the body layer, wherein a disconnected potion of the depletable shield is spaced apart from a connected portion of the depletable shield by a portion of the substrate configured to connect an epitaxial region of the first conductivity type formed proximate to the trenches to a drain contact of the first conductivity type formed in a bottom portion of the substrate.

7. The method of claim 6, wherein the disconnected portion of the depletable shield continuously extends below two or more trenches in the primary plane and is configured to form an orthogonal super-junction structure with the portion of the substrate configured to connect the epitaxial region to the drain contact.

8. The method of claim 1, wherein forming the plurality of trenches includes forming the upper portion of the trench by etching through the openings in the hardmask and the substrate;

growing the upper insulative layer along the sidewalls and bottom surface of the upper portion of the trench and forming spacers on the upper insulative layer along the sidewalls;

forming the bottom portion of the trench by etching through the insulative layer disposed on the bottom surface of the upper portion and through the substrate below the upper portion of the trench using the spacers as a mask;

growing the lower insulative layer along the sidewalls and bottom surface of the bottom portion of the trench; and

removing the spacers.

9. The method of claim 1, wherein forming the plurality of trenches includes forming the upper and lower portions of the trench by etching through the openings in the hardmask and the substrate;

growing the lower insulative layer along the sidewalls and bottom surfaces of the upper and lower portions of the trench;

filling the lower portion of the trench with a first portion of the conductive material;

removing the lower insulative layer from the upper portion of the trench;

growing the upper insulative layer along the sidewalls of the upper portion of the trench and along a top surface of the conductive material in the lower portion of the trench;

forming spacers with a second portion of the conductive material on the upper insulative layer along the sidewalls; and

etching away the upper insulative layer from the top surface of the conductive material in the lower portion of the trench.

10. The method of claim 1, further comprising:

forming a source layer of the first conductivity type in a top portion of the substrate.

11. The method of claim 1, wherein forming the plurality of trenches in the substrate further includes forming one or more gate pickup trenches.

12. The method of claim 11, wherein disposing a conductive material in the trenches further includes disposing the conductive material in the gate pickup trenches to form gate pickup electrodes.

13. The method of claim 11, wherein the one or more gate pickup trenches are formed in a doped tub of the second conductivity type that is formed in the semiconductor substrate.

14. The method of claim 1, further comprising:

forming an electrostatic discharge (ESD) protection electrode above the first layer of the hard mask before it is removed by depositing a layer of conductive material over the first layer of the hardmask and by applying an ESD mask and an ESD etching process.

15. The method of claim 14, further comprising oxidizing the surface of the ESD protection electrode before removing the second layer of the hardmask.

16. The method of claim 1, further comprising:

forming one or more Schottky contacts configured to terminate the device.

17. The method of claim 16, wherein forming the Schottky contact further includes forming one or more body clamp (BCL) structures.

18. The method of claim 1, wherein openings into the semiconductor substrate for source contacts are formed sufficiently close to each other that active devices in the MOSFET device have a pitch of less than 1.0 microns.

19. The method of claim 18, wherein openings into the semiconductor substrate for source contacts are formed sufficiently close to each other that active devices in the MOSFET device have a pitch of less than 0.6 microns.

20. The method of claim 1, further comprising:

forming an ohmic contact region proximate to the openings into the semiconductor substrate for the source contacts, wherein the ohmic contact region has a high dopant concentration of dopants of the second conductivity type.