Three-dimensional semiconductor architecture

• US 8,753,939 B2
• Filed: 08/02/2013
• Issued: 06/17/2014
• Est. Priority Date: 04/07/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Law, Oscar M. K., Wu, Kuo H.
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US13/957,701
• Publication Number:
  US 20130316530A1
• Time in Patent Office: 319 Days
• Field of Search: 257/774, 257/776, 257/E23.067, 438/280
• US Class Current: 438/280
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

manufacturing a plurality of active devices at least partially within a first side of a substrate, the substrate having a peripheral region and an interior region surrounded by the peripheral region;

forming a first set of conductive vias entirely through the substrate in the peripheral region; and

forming a second set of conductive vias entirely through the substrate in the interior region, wherein the second set of conductive vias are part of a power matrix.

2. The method of claim 1, wherein the second set of conductive vias are located in a line that separates a second side of the substrate into a first section and a second section.

3. The method of claim 2, further comprising forming a third set of conductive vias in a line that separates the second section of the substrate into a third section and a fourth section.

4. The method of claim 1, further comprising manufacturing redistribution lines on a second side of the substrate and in electrical connection to the second set of conductive vias.

5. The method of claim 1, further comprising:

forming metallization layers over the first side of the substrate; and

forming a continuous passivation layer over the metallization layers.

6. The method of claim 1, wherein the first set of conductive vias and the second set of conductive vias are all either power connections or ground connections.

7. The method of claim 1, wherein the forming the second set of conductive vias forms the second set of conductive vias into at least a first line and a second line, wherein the first line is parallel to a first side of the substrate and the second line is perpendicular to and separated from the first line.

8. A method of manufacturing a semiconductor device, the method comprising:

forming active devices at least partially within a first side of a substrate, the substrate having a second side opposite the first side;

forming a dielectric layer over the first side;

forming conductive vias all the way through the substrate and the dielectric layer;

depositing a conductive metallization region over the conductive vias and the active devices, the conductive metallization region in physical contact with at least one of the conductive vias and in electrical contact with at least one of the active devices; and

forming a power matrix on the second side of the substrate in electrical contact with at least one of the conductive vias.

9. The method of claim 8, wherein the conductive vias are all either power connections or ground connections.

10. The method of claim 9, wherein the conductive vias are arranged in an array of rows and columns.

11. The method of claim 9, wherein the forming the power matrix further comprises:

forming a redistribution layer electrically connected to the conductive vias; and

forming exterior connections electrically connected to the redistribution layer.

12. The method of claim 11, wherein the forming the redistribution layer further comprises forming power redistribution lines and ground redistribution lines arranged in alternating rows.

13. The method of claim 11, wherein each exterior connection is located over individual ones of the conductive vias.

14. The method of claim 13, wherein each exterior connection is located over a conductive via that is adjacent to no more than one other conductive via located under another exterior connection.

15. The method of claim 8, wherein the metallization region comprises a plurality of metallization layers, and an uppermost metallization layer comprises a signal contact pad.

16. A method of manufacturing a semiconductor device, the method comprising:

forming active devices on a first side of a substrate, the active devices being formed at least partially within the substrate

forming a dielectric layer over the active devices;

forming conductive vias through the dielectric layer and at least partially through the substrate;

forming a metallization layer over the dielectric layer, the metallization layer comprising at least one conductive region in electrical connection with at least one active device;

exposing the conductive vias through a second side of the substrate opposite the first side such that the conductive vias being in electrical contact with at least one active device extends from the first side to the second side; and

forming a power matrix on the second side of the substrate, the power matrix being in physical contact with the conductive vias.

17. The method of claim 16, wherein the conductive vias are all either power connections or ground connections.

18. The method of claim 16, further comprising:

forming a redistribution layer in electrical contact with the conductive vias; and

forming exterior connections in electrical contact with the redistribution layer.

19. The method of claim 18, wherein the forming the redistribution layer further comprising forming power redistribution lines and ground redistribution lines in alternating rows.

20. The method of claim 18, wherein the forming exterior connections is performed such that each exterior connection is located over a conductive via that is adjacent to no more than one other conductive via located under another exterior connection.