Field-effect transistor, and memory and semiconductor circuit including the same

• US 8,754,409 B2
• Filed: 03/23/2012
• Issued: 06/17/2014
• Est. Priority Date: 03/25/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Godo, Hiromichi, Takemura, Yasuhiko
• Primary Examiner(s): Le, Dung Anh
• Application Number:
  US13/428,008
• Publication Number:
  US 20120241739A1
• Time in Patent Office: 816 Days
• Field of Search: 257/43, 257/57, 257/59, 257/72, 257/347, 257/288, 257/310, 257/646, 257/350
• US Class Current: 257/43
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced.

Claims

1. A semiconductor device comprising:

a circuit comprising a transistor, the transistor comprising;

an oxide semiconductor being substantially perpendicular to an insulating surface, wherein the oxide semiconductor has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, and has a height of greater than or equal to a minimum feature size used to form the circuit;

a gate insulating film covering the oxide semiconductor; and

a strip-like gate covering the gate insulating film and facing at least three surfaces of the oxide semiconductor, wherein the strip-like gate has a width of greater than or equal to 10 nm and less than or equal to 100 nm.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—

Zn-based oxide, a Sn—

Zn-based oxide, an Al—

Zn-based oxide, a Zn—

Mg-based oxide, a Sn—

Mg-based oxide, an In—

Mg-based oxide, an In—

Sn-based oxide, an In—

Ga-based oxide, an In—

Ga—

Zn-based oxide, an In—

Sn—

Zn-based oxide, an In—

Al—

Zn-based oxide, a Sn—

Ga—

Zn-based oxide, an Al—

Ga—

Zn-based oxide, a Sn—

Al—

Zn-based oxide, and an In—

Sn—

Ga—

Zn-based oxide.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor has crystallinity.

10. The semiconductor device according to claim 1, wherein part of the oxide semiconductor comprises a region comprising nitrogen, boron, or phosphorus.

13. A random access memory comprising the transistor according to claim 1 as a cell transistor.

16. A memory comprising the transistor according to claim 1 as a writing transistor.

21. The semiconductor device according to claim 1, wherein a corner portion of the oxide semiconductor has a curved shape.

2. A semiconductor device comprising:

a circuit comprising a transistor, the transistor comprising;

an oxide semiconductor being substantially perpendicular to an insulating surface, wherein the oxide semiconductor has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, and has a height of greater than or equal to a minimum feature size used to form the circuit;

a gate insulating film covering the oxide semiconductor; and

a gate covering the gate insulating film and facing at least three surfaces of the oxide semiconductor.

5. The semiconductor device according to claim 2, wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—

Zn-based oxide, a Sn—

Zn-based oxide, an Al—

Zn-based oxide, a Zn—

Mg-based oxide, a Sn—

Mg-based oxide, an In—

Mg-based oxide, an In—

Sn-based oxide, an In—

Ga-based oxide, an In—

Ga—

Zn-based oxide, an In—

Sn—

Zn-based oxide, an In—

Al—

Zn-based oxide, a Sn—

Ga—

Zn-based oxide, an Al—

Ga—

Zn-based oxide, a Sn—

Al—

Zn-based oxide, and an In—

Sn—

Ga—

Zn-based oxide.

8. The semiconductor device according to claim 2, wherein the oxide semiconductor has crystallinity.

11. The semiconductor device according to claim 2, wherein part of the oxide semiconductor comprises a region comprising nitrogen, boron, or phosphorus.

14. A random access memory comprising the transistor according to claim 2 as a cell transistor.

17. A memory comprising the transistor according to claim 2 as a writing transistor.

22. The semiconductor device according to claim 2, wherein a corner portion of the oxide semiconductor has a curved shape.

3. A semiconductor device comprising:

a circuit comprising a transistor, the transistor comprising;

an oxide semiconductor being substantially perpendicular to an insulating surface, wherein the oxide semiconductor has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, and has a height of greater than or equal to a minimum feature size used to form the circuit;

two separated conductors, each covering the oxide semiconductor and facing at least three surfaces of the oxide semiconductor;

a gate insulating film covering the oxide semiconductor; and

a gate covering the gate insulating film and facing at least three surfaces of the oxide semiconductor.

6. The semiconductor device according to claim 3, wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In—

Zn-based oxide, a Sn—

Zn-based oxide, an Al—

Zn-based oxide, a Zn—

Mg-based oxide, a Sn—

Mg-based oxide, an In—

Mg-based oxide, an In—

Sn-based oxide, an In—

Ga-based oxide, an In—

Ga—

Zn-based oxide, an In—

Sn—

Zn-based oxide, an In—

Al—

Zn-based oxide, a Sn—

Ga—

Zn-based oxide, an Al—

Ga—

Zn-based oxide, a Sn—

Al—

Zn-based oxide, and an In—

Sn—

Ga—

Zn-based oxide.

9. The semiconductor device according to claim 3, wherein the oxide semiconductor has crystallinity.

12. The semiconductor device according to claim 3, wherein part of the oxide semiconductor comprises a region comprising nitrogen, boron, or phosphorus.

15. A random access memory comprising the transistor according to claim 3 as a cell transistor.

18. A memory comprising the transistor according to claim 3 as a writing transistor.

19. The semiconductor device according to claim 3, wherein the gate does not overlap with the two separated conductors.

20. The semiconductor device according to claim 19, further comprising a N-type region provided in a part of the oxide semiconductor, wherein the part of the oxide semiconductor is not overlapped with the gate or the two separated conductors.

23. The semiconductor device according to claim 3, wherein a corner portion of the oxide semiconductor has a curved shape.