Intra die variation monitor using through-silicon via

• US 8,754,412 B2
• Filed: 01/03/2012
• Issued: 06/17/2014
• Est. Priority Date: 01/03/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yu, Xiaojun, Mocuta, Anda C., Kirihata, Toshiaki
• Primary Examiner(s): ULLAH, ELIAS
• Application Number:
  US13/342,226
• Publication Number:
  US 20130168673A1
• Time in Patent Office: 896 Days
• Field of Search: 257/48, 257/E21.531, 257/E23.001, 257/786, 257/758, 257/777, 438/18
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.

Claims

1. An apparatus comprising:

at least two intra die variation monitors (IDVMONs);

at least two through silicon vias (TSVs), wherein each of the at least two IDVMONs are embedded in each of the at least two TSVs; and

at least two probe pads located on a backside of a wafer, wherein the at least two TSVs connect the at least two IDVMONs to the at least two probe pads.

2. The apparatus of claim 1 wherein the IDVMON is located in the kerf of the wafer.

3. The apparatus of claim 1 where in the through silicon vias are annular vias and the IDVMON is located within the center of one of the through silicon vias.

4. The apparatus of claim 1 wherein the IDVMON comprises at least one resistive element.

5. The apparatus of claim 1 wherein the IDVMON comprises at least one diode.

6. The apparatus of claim 1 wherein the IDVMON comprises a ring oscillator.

7. The apparatus of claim 1 wherein the IDVMON comprises a transistor.