Semiconductor device and method of manufacturing the same

• US 8,754,433 B2
• Filed: 12/07/2012
• Issued: 06/17/2014
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsui, Yukiteru, Minamihaba, Gaku, Eda, Hajime, Amano, Minoru, Yoshikawa, Masatoshi, Sato, Motoyuki, Suguro, Kyoichi, Kodera, Masako, Iwayama, Masayoshi
• Primary Examiner(s): Nguyen, Dao H
• Assistant Examiner(s): Nguyen, Tram H
• Application Number:
  US13/708,798
• Publication Number:
  US 20130095656A1
• Time in Patent Office: 557 Days
• Field of Search: 257664-677, 257734-786, 257E21537-E21539, 257E29111-E29165, 257E2301-E23079, 257E23141-E23179, 257E29116-E29122, 257/E29.284, 257/E29.299, 257/E21.432, 257E21135-E2121, 257/E21.627, 257/E21.641, 257/E21.44, 257E21619-E2162, 257E21575-E21597, 257/41, 257/81, 257/82, 257/91, 257/99, 257177-182, 257/276, 257/457, 257/459, 257/502, 257/503, 257/573, 257/284, 257/621, 257688-700, 257734-786, 257E2301-E23079, 257E23141-E23179, 257/295, 257/421, 257/E29.167, 257/E29.272, 257/E29.323, 257/E21.436, 257E21663-E21665, 257/E27.104, 257296-313, 257/533, 257595-602, 257923-924, 257E27016-E27017, 257E27019-E27021, 257E27023-E27025, 257E2703-E27035, 257E27037-E27038, 257E27041-E27045, 257E27047-E27048, 257E27071-E2709, 257/E27.092, 257/E27.093, 257/E27.095, 257/E27.101, 257E27114-E27116, 438/171, 438/190, 438/210, 438238-253, 438/329, 438/379, 438/387, 438/444, 438/901
• US Class Current: 257/98
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a contact plug by

forming a first metal material; and

polishing the first metal material by a first CMP-process and a second CMP-process until a roughness of an upper surface of the contact plug becomes 0.2 nm or less, and

wherein the second CMP-process is executed by using an acid-slurry comprising a colloidal silica, and

the colloidal silica comprises silica particles.

2. The method of claim 1,

wherein the forming the contact plug is repeated twice or more.

3. The method of claim 1, further comprising:

forming a functional element on a lower electrode after forming the lower electrode on the contact plug,

wherein the forming the lower electrode comprises polishing a second metal material by the second CMP-process after forming the second metal material on the contact plug.

4. The method of claim 1, further comprising:

forming a functional element on a lower electrode after forming the lower electrode on the contact plug,

wherein the forming the lower electrode comprises smoothing a second metal material by a gas cluster ion beam method after forming the second metal material on the contact plug.

5. The method of claim 1,

wherein a diameter of each of the silica particles is 100 nm or less.

6. The method of claim 2,

wherein a diameter of each of the silica particles is 100 nm or less.

7. The method of claim 3,

wherein a diameter of each of the silica particles is 100 nm or less.

8. The method of claim 4,

wherein a diameter of each of the silica particles is 100 nm or less.