Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure

• US 8,754,455 B2
• Filed: 01/03/2011
• Issued: 06/17/2014
• Est. Priority Date: 01/03/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Xuefeng, Phelps, Richard A., Rassel, Robert M., Tian, Xiaowei
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Ligai, Maria
• Application Number:
  US12/983,489
• Publication Number:
  US 20120168820A1
• Time in Patent Office: 1,261 Days
• Field of Search: 257/192, 257/256, 257/E21.403, 257/E21.407, 257/E21.421, 438/186
• US Class Current: 257/256
• CPC Class Codes: H01L 27/14679 Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/8086 Thin film JFET's

Abstract

Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

Claims

1. A junction field effect transistor comprising:

an N-type channel region comprising a first semiconductor material, having a first end and a second end opposite said first end, and further having a first side and a second side opposite said first side;

N-type source/drain regions adjacent to said first end and said second end and comprising said first semiconductor material;

a first P-type gate adjacent to said first side comprising said first semiconductor material; and

a second P-type gate adjacent to said second side, said second P-type gate comprising a second semiconductor material different from said first semiconductor material, said second semiconductor material comprising any one of silicon germanium and silicon germanium carbide so as to limit P-type dopant out-diffusion into said N-type channel region.

2. The junction field effect transistor of claim 1, further comprising:

a substrate;

an insulator layer on said substrate; and

an N-type semiconductor layer on said insulator layer,

said N-type source/drain regions comprising N-type implant regions in said semiconductor layer,

said N-type channel region comprising a portion of said semiconductor layer separating said N-type implant regions,

said first P-type gate comprising any one of a first P-type silicon germanium layer and a first P-type silicon germanium carbide layer filling a first trench that is positioned laterally adjacent to said first side of said N-type channel region, and

said second P-type gate comprising any one of the following;

a P-type implant region adjacent to said second side of said N-type channel region; and

any one of a second P-type silicon germanium layer and a second P-type silicon germanium carbide layer filling a second trench that is positioned laterally adjacent to said second side of said N-type channel region.

3. The junction field effect transistor of claim 1, further comprising:

a silicon substrate; and

a first N-well in said substrate,

said first P-type gate comprising a P-well in said substrate above and abutting said first N-well,

said N-type channel region comprising a second N-well in said substrate above and abutting said P-well, and

said second P-type gate comprising any one of a P-type silicon germanium layer and a P-type silicon germanium carbide layer filling a trench that extends vertically from a top surface of said substrate to said second N-well, said trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate.

4. The junction field effect transistor of claim 3,

said N-type source/drain regions comprising N-type implant regions at said top surface of said substrate and abutting said N-type channel region,

said N-type implant regions having a higher concentration of an N-type dopant than said N-type channel region,

said second P-type gate being positioned laterally between said N-type implant regions, and

said field effect transistor further comprising isolation structures isolating said N-type implant regions from said second P-type gate.

5. The junction field effect transistor of claim 4, further comprising:

a first contact extending vertically from said top surface to said first P-type gate; and

a second contact extending vertically from said top surface to said first N-well.

6. A junction field effect transistor comprising:

an N-type channel region comprising a first semiconductor material, having a first end and a second end opposite said first end, and further having a first side and a second side opposite said first side, said first semiconductor material comprising silicon;

N-type source/drain regions adjacent to said first end and said second end and comprising said first semiconductor material;

a first P-type gate adjacent to said first side and comprising said first semiconductor material; and

a second P-type gate adjacent to said second side and comprising a second semiconductor material different from said first semiconductor material, said second semiconductor material comprising any one of silicon germanium and silicon germanium carbide so as to limit P-type dopant out-diffusion into said N-type channel region.

7. The junction field effect transistor of claim 6, further comprising:

a silicon substrate; and

a first N-well in said substrate,

said first P-type gate comprising a P-well in said substrate above and abutting said first N-well,

said N-type channel region comprising a second N-well in said substrate above and abutting said P-well, and

said second P-type gate comprising any one of a P-type silicon germanium layer and a P-type silicon germanium carbide layer filling a trench that extends vertically from a top surface of said substrate to said second N-well, said trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate.

8. The junction field effect transistor of claim 7,

said N-type source/drain regions comprising N-type implant regions at said top surface of said substrate and abutting said N-type channel region,

said N-type implant regions having a higher concentration of an N-type dopant than said N-type channel region,

said second P-type gate being positioned laterally between said N-type implant regions, and

said field effect transistor further comprising isolation structures isolating said N-type implant regions from said second P-type gate.

9. The junction field effect transistor of claim 8, further comprising:

a first contact extending vertically from said top surface to said first P-type gate; and

a second contact extending vertically from said top surface to said first N-well.

10. The junction field effect transistor of claim 6, further comprising:

a silicon substrate; and

an N-well in said substrate,

said first P-type gate comprising any one of a first P-type silicon germanium layer and a first P-type silicon germanium carbide layer in a lower portion of a first trench that extends vertically from a top surface of said substrate to said N-well,

said N-type channel region comprising an N-type silicon layer in said first trench on said first P-type gate, and

said second P-type gate comprising a P-type semiconductor layer filling a second trench that extends vertically into said N-type silicon layer, said second trench having a bottom surface that abuts said N-type channel region and is above and physically separated from said first P-type gate.

11. The junction field effect transistor of claim 10, said P-type semiconductor layer comprising any one of a P-type silicon layer, a second P-type silicon germanium layer and a second P-type silicon germanium carbide layer.

12. The junction field effect transistor of claim 10,

said N-type source/drain regions comprising N-type implant regions at said top surface of said substrate abutting said N-type channel region,

said N-type implant regions having a higher concentration of an N-type dopant than said N-type channel region,

said second P-type gate being positioned laterally between said N-type implant regions, and

said field effect transistor further comprising isolation structures isolating said N-type implant regions from said second P-type gate.

13. The junction field effect transistor of claim 10, further comprising:

a first contact extending vertically from said top surface to said first P-type gate; and

a second contact extending vertically from said top surface to said N-well.

14. A junction field effect transistor comprising:

a substrate having a top surface and comprising;

a first N-well;

a P-well above and abutting said first N-well, said P-well being a first P-type gate;

a second N-well above and abutting said P-well, said second N-well being an N-type channel region having a first end and a second end opposite said first end, and further having a first side adjacent to said first P-type gate and a second side opposite said first side; and

,

N-type implant regions extending vertically from said top surface to said first end and to said second end of said N-type channel region,

said N-type implant regions being N-type source/drain regions,

said substrate comprising a first semiconductor material such that said first P-type gate and said N-type channel region comprise said first semiconductor material, and

said first semiconductor material comprising silicon;

a trench in said substrate positioned laterally between said N-type source/drain regions and extending vertically from said top surface of said substrate to said second side of said N-type channel region;

a P-type epitaxial semiconductor layer filling said trench,

said P-type epitaxial semiconductor layer being a second P-type gate on said second side of said N-type channel region,

said P-type epitaxial semiconductor layer comprising a second semiconductor material that is different from said first semiconductor material, and

said second semiconductor material comprising any one of silicon germanium and silicon germanium carbide so as to limit P-type dopant out-diffusion into said N-type channel region; and

,

an isolation structure electrically isolating said second P-type gate from said N-type source/drain regions.

15. The junction field effect transistor of claim 14, said N-type implant regions having a higher concentration of an N-type dopant than said N-type channel region.

16. The junction field effect transistor of claim 14, further comprising:

a first contact extending vertically from said top surface to said first P-type gate; and

a second contact extending vertically from said top surface to said first N-well.

17. A junction field effect transistor comprising:

a substrate having a top surface and comprising an N-well below said top surface, said substrate comprising a first semiconductor material comprising silicon;

a first trench extending vertically from said top surface to said N-well;

a first P-type epitaxial semiconductor layer in a lower portion of said first trench, said first P-type epitaxial semiconductor layer being a first P-type gate and comprising a second semiconductor material that is different from said first semiconductor material;

an N-type epitaxial semiconductor layer in an upper portion of said first trench above said first P-type epitaxial semiconductor layer,

said N-type epitaxial semiconductor layer being an N-type channel region having a first end and a second end opposite said first end, and further having a first side adjacent to said first P-type gate and a second side opposite said first side,

said N-type epitaxial semiconductor layer comprising said first semiconductor material, and

said second semiconductor material comprising any one of silicon germanium and silicon germanium carbide so as to limit P-type dopant out-diffusion into said N-type channel region;

a second trench extending vertically into said N-type epitaxial semiconductor layer and having a bottom surface that is above and physically separated from said first P-type gate;

a second P-type epitaxial semiconductor layer filling said second trench, said second P-type epitaxial semiconductor layer being a second P-type gate on said second side of said N-type channel region,

said second P-type epitaxial semiconductor layer comprising a different semiconductor material than said first P-type epitaxial semiconductor layer,

said substrate further comprising N-type implant regions at said top surface abutting said first end and said second end of said N-type channel region, and

said N-type implant regions being N-type source/drain regions; and

,

an isolation structure electrically isolating said second P-type gate from said N-type source/drain regions.

18. The junction field effect transistor of claim 17, said N-type implant regions having a higher concentration of an N-type dopant than said N-type channel region.

19. The junction field effect transistor of claim 17, further comprising:

a first contact extending vertically from said top surface to said first P-type gate; and

a second contact extending vertically from said top surface to said N-well.