Self aligned borderless contact

• US 8,754,527 B2
• Filed: 07/31/2012
• Issued: 06/17/2014
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Sreenivasan, Rahhavasimhan
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): MUSE, ISMAIL A
• Application Number:
  US13/562,341
• Publication Number:
  US 20140035141A1
• Time in Patent Office: 686 Days
• Field of Search: 257/316, 257/369, 257/774, 216/67, 438/305, 438/643, 438/660
• US Class Current: 257/751
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76823 transforming an insulating layer into a conductive layer
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a semiconductor structure having a borderless contact, the method including providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate, depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, depositing a contact level dielectric layer on top of the non-conductive liner, etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, converting a portion of the non-conductive liner exposed in the contact hole into a conductive liner; and forming a metal contact in the contact hole.

Claims

1. A method of fabricating a semiconductor structure having a borderless contact, the method comprising:

providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate;

depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices;

depositing a contact level dielectric layer on top of the non-conductive liner;

etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner, to expose a first portion of the non-conductive liner;

depositing a nitrogen absorption layer on top of the first portion of the non-conductive liner exposed within the contact hole; and

performing a thermal anneal causing the nitrogen absorption layer to absorb nitrogen from the non-conductive liner, and causing an entire thickness of the first portion of the non-conductive liner to change from an insulator to a conductor.

2. The method of claim 1, wherein the non-conductive liner is Ta₃N₅.

3. The method of claim 1, wherein the conductive liner is TaN.

4. The method of claim 1, wherein performing the thermal anneal comprises changing the non-conductive liner from Ta₃N₅ to TaN.

5. The method of claim 1, wherein the nitrogen absorption layer comprises titanium, tungsten or zirconium.

6. A method of fabricating a semiconductor structure having a borderless contact, the method comprising:

providing a first semiconductor device adjacent to a second semiconductor device, the first and second semiconductor devices being formed on a semiconductor substrate;

depositing a non-conductive liner on top of the semiconductor substrate and the first and second semiconductor devices, the non-conductive liner comprising ruthenium-nitride;

depositing a contact level dielectric layer on top of the non-conductive liner;

etching a contact hole in the contact-level dielectric between the first semiconductor device and the second semiconductor device, and selective to the non-conductive liner to expose a first portion of the non-conductive liner; and

converting an entire thickness of the first portion of the non-conductive liner exposed in the contact hole into a conductive liner.

7. The method of claim 6, wherein converting the entire thickness of the first portion of the non-conductive liner exposed in the contact hole into a conductive liner comprises:

performing a plasma bombardment technique on the portion of the non-conductive liner exposed in the contact hole, and causing the portion of the non-conductive liner to change from an insulator to a conductor.

8. The method of claim 6, wherein converting the entire thickness of the first portion of the non-conductive liner exposed in the contact hole into a conductive liner comprises:

depositing a nitrogen absorption layer on top of the first portion of the non-conductive liner exposed within the contact hole; and

performing a thermal anneal causing the nitrogen absorption layer to absorb nitrogen from the non-conductive nitride liner, and causing the entire thickness of the first portion of the non-conductive liner to change from an insulator to a conductor.