Semiconductor device

• US 8,754,534 B2
• Filed: 11/09/2012
• Issued: 06/17/2014
• Est. Priority Date: 02/08/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shinohara, Minoru, Araki, Makoto, Sugiyama, Michiaki
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/673,990
• Publication Number:
  US 20130069249A1
• Time in Patent Office: 585 Days
• Field of Search: 257/E23.01, 257/E23.169, 257/685, 257/686, 257/723, 257/777, 257/784, 257/E21.614, 257/E25.013, 438107-109, 361/760
• US Class Current: 257/777
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/5388 : for flat cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Claims

1. A semiconductor device in which a plurality of memory chips are mounted in a stacked manner on a main surface of a wiring board, wherein:

the plurality of memory chips includes at least four memory chips,

each of the plurality of memory chips has a front main surface facing away from the wiring board and a rear main surface opposite the front main surface and facing toward the wiring board,

the front main surface of each of the plurality of memory chips has a respective first side,

respective first terminals are formed on the first side of the front main surface of each of the plurality of memory chips,

the plurality of memory chips are stacked in a dislocated manner along a direction perpendicular to the first side of each front main surface so that the first terminals provided on the first side of each front main surface are exposed from other memory chips of the plurality,

the first side of a memory chip of a lowermost layer of the plurality of memory chips is disposed in line with a first side of the wiring board,

a number of the memory chips dislocated continuously in a same direction is at least two,

except for a memory chip of an uppermost layer in the plurality of memory chips, a memory chip of an uppermost layer in a group of the memory chips dislocated continuously in the same direction is stacked in a state of being rotated 180°

degrees from each other memory chip in the group,

an interposer is provided on the memory chip of the uppermost layer of the plurality of memory chips,

the interposer is connected to a memory chip having the first terminals thereof disposed toward the first side of the wiring board or a memory chip having second terminals on a side opposite to the first side of the wiring board through first wires,

the interposer is further connected to the wiring board through second wires,

a memory controller chip for controlling the memory chips is provided on the interposer, and

the memory controller chip is electrically connected to the interposer.