Voltage conversion and integrated circuits with stacked voltage domains

• US 8,754,672 B2
• Filed: 03/14/2012
• Issued: 06/17/2014
• Est. Priority Date: 04/13/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dennard, Robert H., Ji, Brian L.
• Primary Examiner(s): Taningco, Alexander H
• Assistant Examiner(s): LO, CHRISTOPHER KWOK YEUNG
• Application Number:
  US13/420,080
• Publication Number:
  US 20120169319A1
• Time in Patent Office: 825 Days
• Field of Search: 326 62- 65, 326 81- 83, 326 86- 87, 326/112, 326/115, 326/121, 327108-109, 327/333, 330/277, 330290-295
• US Class Current: 326/81
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 19/01806 Interface arrangements
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/00 Circuits for generating electric pulses; Monostable, bistable or multistable circuits H03K4/00 takes precedence; for digital function generators in computers G06F1/02
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

A reversible, switched capacitor voltage conversion apparatus includes a plurality of individual unit cells coupled to one another in stages, with each unit cell comprising multiple sets of inverter devices arranged in a stacked configuration, such that each set of inverter devices operates in separate voltage domains wherein outputs of inverter devices in adjacent voltage domains are capacitively coupled to one another such that a first terminal of a capacitor is coupled to an output of a first inverter device in a first voltage domain, and a second terminal of the capacitor is coupled to an output of a second inverter in a second voltage domain; and wherein, for both the first and second voltage domains, outputs of at least one of the plurality of individual unit cells serve as corresponding inputs for at least another one of the plurality of individual unit cells.

Claims

1. A reversible, switched capacitor voltage conversion apparatus, comprising:

a plurality of individual unit cells coupled to one another in stages, with each unit cell comprising multiple sets of inverter devices arranged in a stacked configuration, such that each set of inverter devices operates in separate voltage domains wherein for each inverter device in each of the plurality of unit cells, outputs of each of the inverter devices in adjacent voltage domains are capacitively coupled to one another such that a first terminal of a capacitor is coupled to an output of a first inverter device in a first voltage domain, and a second terminal of the capacitor is coupled to an output of a second inverter in a second voltage domain;

wherein, for both the first and second voltage domains, a first of the plurality of individual unit cells serve as corresponding inputs for a second of the plurality of individual unit cells, and for both the first and second voltage domains, outputs of the second of the plurality of individual unit cells serve as corresponding inputs for a third of the plurality of individual unit cells; and

for both the first and second voltage domains, outputs of a last of the plurality of individual unit cells comprise inputs to a first of the plurality of individual unit cells in a ring oscillator type structure.

2. The apparatus of claim 1, wherein inputs to the first of the plurality of individual unit cells comprise control signals.

3. The apparatus of claim 1, wherein the inputs to the first of the plurality of individual unit cells are prevented from allowing simultaneous conduction of a PFET device and an NFET device of inverter device in each voltage domain.

4. The apparatus of claim 3, wherein each input to the first of the plurality of individual unit cells is coupled to a buffer device operating in the corresponding voltage domain, with an output of each buffer device serving as inputs to the inverter device in the corresponding voltage domain.

5. The apparatus of claim 4, further comprising, for each voltage domain, a first buffer device coupled to a PFET of the inverter device and a second buffer device coupled to an NFET of the inverter device.

6. The apparatus of claim 4, wherein the first and second buffer devices each comprise an inverter pair where a first of the inverter pair has a larger NFET/PFET device width ratio and a second of the inverter pair has a larger PFET/NFET device width ratio.