Apparatus and methods for invertible sine-shaping for phase interpolation

• US 8,754,678 B1
• Filed: 03/15/2013
• Issued: 06/17/2014
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Schell, Robert
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US13/835,598
• Time in Patent Office: 459 Days
• Field of Search: 327/105, 327/129, 330/20
• US Class Current: 327/129
• CPC Class Codes: H03B 28/00 Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations analogue function generators for performing computing operations G06G7/26; use of transformers for conversion of waveform in ac-ac converters H02M5/18
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 4/92 having a waveform comprising a portion of a sinusoid generating sinusoidal oscillations H03B
• CPC Class Codes: H04L 7/002 correction by interpolation

Abstract

Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.

Claims

1. An apparatus comprising:

an invertible sine-shaping filter configured to;

receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal;

filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals; and

selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal; and

a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal,

wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.

2. The apparatus of claim 1, wherein the invertible sine-shaping filter comprises a buffer circuit configured to buffer the in-phase clock signal to generate an in-phase sinusoidal reference clock signal and to buffer the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature-phase relationship.

3. The apparatus of claim 1, further comprising a sampler configured to receive a serial data stream and to sample the serial data stream on at least one of a rising edge of a sampling clock signal and a falling edge of the sampling clock signal, wherein the phase interpolator is configured to generate the sampling clock signal based on the interpolated clock signal.

4. The apparatus of claim 3, further comprising an invert logic circuit configured to generate the inversion control signal based on the serial data stream.

5. The apparatus of claim 4, wherein the invert logic circuit is configured to modify the inversion control signal only when a weight value of the phase interpolator is within a threshold range.

6. The apparatus of claim 1, wherein the phase interpolator is further configured to determine one or more weight values based on the serial data stream.

7. The apparatus of claim 1, wherein the in-phase and quadrature-phase clock signals, the sinusoidal in-phase and quadrature-phase clock signals, and the selectively inverted sinusoidal in-phase and quadrature-phase clock signals are differential signals.

8. The apparatus of claim 1, further comprising a polyphase filter configured to receive a sinusoidal clock signal and to generate the in-phase clock signal and the quadrature-phase clock signal based on a sinusoidal clock signal.

9. The apparatus of claim 8, wherein the clock input signal is one of a square wave clock input signal or a rectangular wave clock input signal, wherein the clock input signal has a first period, and wherein the in-phase sinusoidal clock signal and the quadrature-phase sinusoidal clock signal each have a period about equal to the first period, and wherein the in-phase sinusoidal clock signal and the quadrature-phase sinusoidal clock signal have a phase difference about equal to one-quarter of the first period.

10. The apparatus of claim 1, further comprising a regulator configured to generate a regulated voltage, wherein the regulator is configured to power at least a portion of the invertible sine-shaping filter using the regulated voltage.

11. A method of clock signal generation, the method comprising:

filtering in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals;

selectively inverting one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal; and

generating an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal,

wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.

12. The method of claim 11, further comprising:

buffering the in-phase clock signal to generate an in-phase sinusoidal reference clock signal; and

buffering the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal,

wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature-phase relationship.

13. The method of claim 11, further comprising generating a sampling clock signal based on the interpolated clock signal and sampling a serial data stream using the sampling clock signal.

14. The method of claim 13, further comprising generating the inversion control signal based on the serial data stream.

15. The method of claim 14, further comprising modifying the inversion control signal only when a weight value is within a threshold range.

16. The method of claim 11, further comprising determining one or more weight values based on the serial data stream.

17. The method of claim 11, wherein the in-phase and quadrature-phase clock signals, the sinusoidal in-phase and quadrature-phase clock signals, and the selectively inverted sinusoidal in-phase and quadrature-phase clock signals are differential signals.

18. The method of claim 11, further comprising generating an in-phase clock signal and a quadrature-phase clock signal from a sinusoidal clock signal using a polyphase filter.

19. The method of claim 18, wherein the clock input signal is one of a square wave clock input signal or a rectangular wave clock input signal, wherein the clock input signal has a first period, and wherein the in-phase sinusoidal clock signal and the quadrature-phase sinusoidal clock signal each have a period about equal to the first period, and wherein the in-phase sinusoidal clock signal and the quadrature-phase sinusoidal clock signal have a phase difference about equal to one-quarter of the first period.

20. The method of claim 11, further comprising generating a regulated voltage configured to power at least a portion of an invertible sine-shaping filter using the regulated voltage.

21. An apparatus for clock signal generation, comprising:

means for filtering in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals;

means for selectively inverting one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal; and

means for generating an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal,

wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.