Latch circuit and semiconductor device

• US 8,754,693 B2
• Filed: 03/01/2013
• Issued: 06/17/2014
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Nishijima, Tatsuji
• Primary Examiner(s): Chen, Sibin
• Application Number:
  US13/782,640
• Publication Number:
  US 20130229218A1
• Time in Patent Office: 473 Days
• Field of Search: 327199-203, 327208-212, 327/214, 327/215, 327/218
• US Class Current: 327/208
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/015 Modifications of generator to maintain energy constant
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A nonvolatile latch circuit is provided. In the latch circuit, a transistor in which a channel region is formed with an oxide semiconductor, which is a wide band gap semiconductor, is included, and data is stored in a node formed by one terminal of a capacitor and one of a source and a drain of the transistor, and is brought into a floating state when the transistor is turned off. After that, even when charge stored in the node is insufficient at time of restoring the data, charge is supplied by feedback; therefore, time necessary for restoring the data can be shortened and even when the power supply is restarted in the state of storing data, the data can be restored at high speed.

Claims

1. A latch circuit comprising:

a first inverter and a second inverter, each comprising an input terminal and an output terminal;

a diode comprising an anode and a cathode;

a switch comprising a first terminal and a second terminal;

a transistor comprising a source terminal and a drain terminal; and

a capacitor,

wherein the switch is electrically connected in parallel to the diode,

wherein the output terminal of the first inverter is electrically connected to the input terminal of the second inverter through the diode and the switch,

wherein the output terminal of the second inverter is electrically connected to the input terminal of the first inverter, and

wherein one of the source terminal and the drain terminal of the transistor is electrically connected to the cathode of the diode, to the switch and to the input terminal of the second inverter.

2. The latch circuit according to claim 1, wherein the transistor comprises a channel formation region in an oxide semiconductor layer.

3. The latch circuit according to claim 1, wherein the switch is a transmission gate.

4. The latch circuit according to claim 1, wherein the latch circuit is configured to hold a logic state at the other of the source terminal and the drain terminal of the transistor.

5. The latch circuit according to claim 1,

wherein the first inverter comprises an inverter transistor comprising a channel formation region in a layer of a first semiconductor material,

wherein a channel formation region of the transistor is in a layer of a second semiconductor material, and

wherein the first semiconductor material and the second semiconductor material are different.

6. The latch circuit according to claim 1,

wherein the first inverter comprises an inverter transistor comprising a channel formation region in a layer of single crystal silicon,

wherein a channel formation region of the transistor is in a layer of an oxide semiconductor material formed over an insulating layer covering the inverter transistor.

7. The latch circuit according to claim 1, wherein a channel formation region of the transistor is in a layer of a material having a band gap greater than or equal to 2 eV.

8. The latch circuit according to claim 1, wherein the transistor has an off-state current per channel formation region width lower than or equal to 1×

10<sup>−

19</sup> A/μ

m.

9. A latch circuit comprising:

a first switch;

a first inverter comprising an input terminal electrically connected to a terminal of the first switch;

a diode comprising an anode and a cathode, the anode being electrically connected to an output terminal of the first inverter at a node (A);

a first transistor comprising a source terminal and a drain terminal, one of the source terminal and the drain terminal being electrically connected to the cathode of the diode at a node (B);

a capacitor electrically connected to the other of the source terminal and the drain terminal of the first transistor;

a second switch electrically connected in parallel with the diode between the node (A) and the node (B);

a second transistor comprising a source terminal and a drain terminal, one of the source terminal and the drain terminal being electrically connected to the node (B);

a second inverter comprising an input electrically connected to the node (B); and

a third switch electrically connecting an output of the second inverter to the terminal of the first switch and to the input of the first inverter.

10. The latch circuit according to claim 9, wherein the second switch is a transmission gate.

11. The latch circuit according to claim 9, wherein the latch circuit is configured to hold a logic state at a node formed by the other of the source terminal and the drain terminal of the first transistor and the capacitor.

12. The latch circuit according to claim 9,

wherein a channel formation region of the first transistor is formed in a layer of a first semiconductor material,

wherein a channel formation region of the second transistor is formed in a layer of a second semiconductor material, and

wherein the first semiconductor material and the second semiconductor material are different.

13. The latch circuit according to claim 9,

wherein a channel formation region of the second transistor is formed in a layer of single crystal silicon, and

wherein a channel formation region of the first transistor is formed in a layer of an oxide semiconductor material formed over an insulating layer covering the second transistor.

14. The latch circuit according to claim 9, wherein a channel formation region of the first transistor is in a layer of a material having a band gap greater than or equal to 2 eV.

15. The latch circuit according to claim 9, wherein the first transistor has an off-state current per channel formation region width lower than or equal to 1×

10<sup>−

19</sup> A/μ

m.

16. A latch circuit comprising:

a first switch;

a first inverter comprising an input terminal electrically connected to a terminal of the first switch;

a diode comprising an anode and a cathode, the anode being electrically connected to an output terminal of the first inverter at a node (A);

a first transistor comprising a source terminal and a drain terminal, one of the source terminal and the drain terminal being electrically connected to the cathode of the diode at a node (B);

a capacitor electrically connected to the other of the source terminal and the drain terminal of the first transistor;

a second switch electrically connected in parallel with the diode between the node (A) and the node (B);

a second transistor comprising a source terminal and a drain terminal, one of the source terminal and the drain terminal being electrically connected to the node (B);

a second inverter comprising an input electrically connected to the node (B); and

a third switch electrically connecting an output of the second inverter to the terminal of the first switch and to the input of the first inverter,

wherein the first transistor comprises a channel formation region in an oxide semiconductor layer.

17. The latch circuit according to claim 16, wherein the second switch is a transmission gate.

18. The latch circuit according to claim 16, wherein the latch circuit is configured to hold a logic state at a node formed by the other of the source terminal and the drain terminal of the first transistor and the capacitor.

19. The latch circuit according to claim 16,

wherein a channel formation region of the first transistor is formed in a layer of a first semiconductor material,

wherein a channel formation region of the second transistor is formed in a layer of a second semiconductor material, and

wherein the first semiconductor material and the second semiconductor material are different.

20. The latch circuit according to claim 16,

wherein the oxide semiconductor layer of the first transistor is formed over an insulating layer covering the second transistor, and

wherein the oxide semiconductor layer of the first transistor is formed in a semiconductor material different from a semiconductor material in which the channel formation region of the second transistor is formed.

21. The latch circuit according to claim 16, wherein the oxide semiconductor layer is formed from a material having a band gap greater than or equal to 2 eV.

22. The latch circuit according to claim 16, wherein the first transistor has an off-state current per channel formation region width lower than or equal to 1×

10<sup>−

19</sup> A/μ

m.