Correlated double-sample differencing within an ADC

• US 8,754,799 B2
• Filed: 08/02/2012
• Issued: 06/17/2014
• Est. Priority Date: 01/27/2012
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Coln, Michael, Carreau, Gary, Kusuda, Yoshinori
• Primary Examiner(s): WILLIAMS, HOWARD L
• Application Number:
  US13/565,082
• Publication Number:
  US 20130194118A1
• Time in Patent Office: 684 Days
• Field of Search: 341/141, 341/155, 341/161, 341/162, 341/163, 341/172, 348/241, 348/243, 348/257, 348294-297, 348/308
• US Class Current: 341/163
• CPC Class Codes: H03M 1/0682 using a differential network structure, i.e. symmetrical with respect to ground
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/124 Sampling or signal conditioning arrangements specially adapted for A/D converters
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling

Abstract

A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.

Claims

1. Apparatus for performing correlated double sampling, comprising:

a signal sampling stage comprising an amplifier with feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, the storage capacitors to store signal and reset values from a sensor respectively,

a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage,

a register to store a programmable value representing a nominal reset voltage,

and a digital to analog converter having an input coupled to the register and an output coupled to the amplifier of the signal sampling stage.

2. The apparatus of claim 1, wherein the differential ADC is part of a circuit stage that further comprises a pair of sample and hold amplifiers (SHA), one SHA provided on each input of the differential ADC and coupled to a respective storage capacitor of the signal sampling stage.

3. The apparatus of claim 1, wherein the differential ADC is a successive approximation register ADC and comprises:

first and second capacitor arrays coupled respectively to one of the storage capacitors of the signal sampling stage,

a comparator having inputs coupled respectively to outputs of the first and second capacitor arrays, and

a register to store bit decisions of the comparator in respective bit positions thereof.

4. The apparatus of claim 1, further comprising a multiplexer provided between an output of the sampling stage and inputs of the differential ADC.

5. The apparatus of claim 1, further comprising a pixel array having an output coupled to the sampling stage.

6. The apparatus of claim 5, wherein the pixel array, the sampling stage and the differential ADC are provided on a common integrated circuit.

7. The apparatus of claim 5, wherein the sampling stage and the differential ADC are provided on a common integrated circuit, separate from the pixel array.

8. Apparatus for performing correlated double sampling, comprising:

a signal sampling stage comprising a plurality of sampling circuits, each circuit comprising;

an amplifier with feedback capacitor, and

a pair of storage capacitors coupled to an output of the amplifier, the storage capacitors to store signal and reset values from a sensor respectively; and

a conversion stage comprising a plurality of differential analog to digital converters (ADCs) having a pair of inputs;

a multiplexing stage provided between the signal sampling stage and the conversion stage comprising multiplexers to couple the storage capacitors of the signal sampling stage to inputs of the ADCs in response to a control signal;

a register to store a programmable value representing a nominal reset voltage; and

a digital to analog converter having an input coupled to the register and an output coupled to amplifier(s) of the signal sampling stage,

wherein the number of sampling circuits is greater than the number of ADCs.

9. The apparatus of claim 8, wherein the conversion stage further comprises, for each differential ADC, a pair of sample and hold amplifiers (SHA), one SHA provided on each input of the differential ADC and coupled to a respective storage capacitor of the signal sampling stage.

10. The apparatus of claim 8, wherein the differential ADC is a successive approximation register ADC and comprises:

first and second capacitor arrays coupled respectively to one of the storage capacitors of the signal sampling stage,

a comparator having inputs coupled respectively to outputs of the first and second capacitor arrays, and

a register to store bit decisions of the comparator in respective bit positions thereof.

11. The apparatus of claim 8, further comprising

a pixel array having a plurality of outputs,

an input multiplexer stage coupling outputs of the pixel array to inputs of the sampling stage, wherein a number of pixel array outputs is greater than a number of sampling circuits.

12. The apparatus of claim 11, wherein the pixel array, the sampling stage and the conversion stage are provided on a common integrated circuit.

13. The apparatus of claim 11, wherein the sampling stage and the conversion stage are provided on a common integrated circuit, separate from the pixel array.

14. A method for performing correlated double sampling, comprising:

reading a reset value from a sensor circuit to a first storage device via a sampling system that uses a stored programmable value representing a nominal reset voltage for sampling,

reading a signal value from the sensor circuit to a second storage device via the sampling system,

generating a digital code representing an output value of the sensor circuit from a comparison of the reset value and the signal value, and using the stored programmable value representing the nominal reset voltage, the comparison being performed by a common element that performs the generating.

15. The method of claim 14, wherein reading the reset value and reading the signal value includes amplifying the signals.

16. The method of claim 14, further comprising storing the reset value in the sampling system and storing the signal value in the sampling system.

17. The method of claim 14, further comprising integrating a first signal to generate the reset value and integrating a second signal to generate the signal value in the sampling system.