Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem

• US 8,754,897 B2
• Filed: 11/15/2010
• Issued: 06/17/2014
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: LucidLogix Software Solutions, Ltd.
• Inventors: Fogel, Efi, Remez, Offir, Bakalash, Reuven
• Primary Examiner(s): NGUYEN, HAU H
• Application Number:
  US12/946,032
• Publication Number:
  US 20110169841A1
• Time in Patent Office: 1,310 Days
• Field of Search: 345/505, 345/519, 345/506, 345/419, 345/520
• US Class Current: 345/519
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06F 3/1423 controlling a plurality of local displays, e.g. CRT and flat panel display
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 2210/52 Parallel processing
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2360/06 Use of more than one graphics processor to process data before displaying to one or more screens
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A silicon chip of a monolithic construction for use in implementing a multiple core graphics processing and display subsystem in a computing system having a CPU, a system memory, an operating system (OS), a CPU bus, and a display device with a display surface. The computing system supports (i) one or more software applications for issuing graphics commands, (ii) one or more graphics libraries for storing data used to implement said graphics commands. The silicon chip comprises multiple graphic pipeline cores, a partial frame buffer for buffering pixels corresponding to image fragments, a routing center, control unit, and a display interface, for displaying composited images on the display surface of the computing system.

Claims

1. A multi-GPU based graphics processing and display system for use within a computing system including an image display device having a display surface, said multi-GPU based graphics processing and display system comprising:

multiple graphics processing unit (GPU) driven pipeline cores wherein each said GPU-driven pipeline core includes a GPU and generates pixel values of images from 3D graphics primitives, associated with at least a portion of a digital image to be displayed on said display surface;

a routing center for distributing graphics data received from a CPU to said multiple GPU driven pipeline cores and for collecting rendering results from said multiple GPU driven pipeline cores,

a processing element (PE) capable of processing graphics data used by said multiple GPU-driven pipeline cores;

a cache memory for serving said processing element, and for caching graphics data; and

a display interface for receiving said rendering results from said routing center and for interfacing with said image display device, so that said generated pixel values of images can be displayed on the display surface of said image display device;

wherein said multiple graphics processing unit (GPU) driven pipeline cores, routing center, said processing element, said cache memory, and said display interface are implemented on a single semiconductor chip, and

wherein said multiple GPU driven pipeline cores are arranged in parallel on said single semiconductor chip to receive graphics data from said routing center according to a parallelization mode.

2. The system of claim 1, wherein each GPU-driven pipeline core receives 3D graphics primitives as input, and generates pixel based images as output.

3. The system of claim 2, wherein said 3D graphics primitives include polygons.

4. The system of claim 1, wherein said router is connected to a system bus.

5. The system of claim 1, wherein said processing element comprises a processor serving the architectural needs of the system.

6. The system of claim 1, wherein said multiple GPU-driven pipeline cores comprises at least four GPU-driven pipeline cores.

7. The system of claim 1, wherein said cache can be used to cache graphics data common to all said GPU-driven pipeline cores.

8. The system of claim 1, wherein said cache can be used to cache textures and vertex objects.

9. The system of claim 1, wherein said display interface is capable of running single or multiple screens.

10. The system of claim 1, wherein each GPU-driven pipeline core comprises a geometry subsystem for processing 3D graphics primitives, and a pixel subsystem for computing pixel values, functionally coupled to each other.

11. The system of claim 1 wherein said single semiconductor chip is of monolithic construction.

12. The system of claim 1 wherein said single semiconductor chip is a silicon chip.