Multiport memory element circuitry
First Claim
1. Memory element circuitry comprising:
- a storage element;
at least one write access transistor coupled to the storage element;
at least one read access transistor coupled to the storage element; and
control circuitry that weakens the at least one read access transistor without weakening the at least write access transistor while loading data into the storage element using the at least one write access transistor during a read-disturb write operation.
3 Assignments
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Accused Products
Abstract
Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.
13 Citations
20 Claims
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1. Memory element circuitry comprising:
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a storage element; at least one write access transistor coupled to the storage element; at least one read access transistor coupled to the storage element; and control circuitry that weakens the at least one read access transistor without weakening the at least write access transistor while loading data into the storage element using the at least one write access transistor during a read-disturb write operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of writing data into a multiport memory element, wherein the multiport memory element comprises a storage element, at least one write access transistor, and at least one read access transistor, the method comprising:
simultaneously weakening the at least one read access transistor and the storage element during each write operation. - View Dependent Claims (14, 15, 16, 17)
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18. A memory element comprising:
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a storage element having at least two transistor pairs, each of which includes a p-channel transistor and an n-channel transistor coupled in series; at least one write address transistor; and at least one read address transistor, wherein the n-channel transistors of the storage element have body bias terminals that receive an adjustable body bias voltage during a read-disturb write in which data is loaded into the storage element, and wherein the at least one write address transistor receives a fixed body bias voltage during the read-disturb write. - View Dependent Claims (19, 20)
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Specification