Efficient pipeline parallelism using frame shared memory

• US 8,755,378 B2
• Filed: 08/21/2012
• Issued: 06/17/2014
• Est. Priority Date: 04/20/2007
• Status: Active Grant

• Current Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Original Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Inventors: Giacomoni, John, Veachharajani, Manish
• Primary Examiner(s): O CONNOR, BRIAN T
• Application Number:
  US13/590,307
• Publication Number:
  US 20130054938A1
• Time in Patent Office: 665 Days
• Field of Search: 370/389, 370/392, 370/419, 709/213, 709/214, 709/215, 709/230
• US Class Current: 370/389
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.

Claims

1. A computer system comprising:

a multi-core processor including a plurality of processing cores;

and

memory communicably coupled with the multi-core processor, wherein the memory stores a plurality of instructions that, when executed by the multi-core processor, cause the multi-core processor to;

allocate a shared memory portion of the memory, wherein the shared memory portion is accessible from kernel space and user space contexts of execution;

process a frame in at least a first stage running in kernel space and a second stage running in user space; and

associate the first and second stages with a point-to-point communication mechanism that allows the first stage and the second stage to exchange data related to the frame through mutual access to the shared memory portion of the memory.

2. The computer system according to claim 1, wherein the memory further includes instructions to extend a processing time of stages with a short processing interval.

3. The computer system according to claim 1, wherein the memory further includes:

instructions to receive the frame through a network interface device; and

instructions to process the frame in each processing stage, wherein a processing time for each stage is about a frame arrival period of the frame.

4. The computer system according to claim 1, wherein the point-to-point communication mechanism includes instructions to use a head pointer without a tail pointer to enqueue.

5. The computer system according to claim 1, wherein the point-to-point communication mechanism includes instructions to use a tail pointer without a head pointer to dequeue.

6. The computer system of claim 1, wherein the first stage occurs at a first processing core of the multi-core processor and the second stage occurs at a second processing core of the multi-core processor.

7. The computer system of claim 1, wherein the point-to-point communication mechanism comprises at least one queue embodied within the shared memory portion and accessible to both user space and kernel space.

8. The computer system of claim 7, wherein the at least one queue embodied within the shared memory portion comprises:

a first queue configured to store data from the frame; and

a second queue configured to store pointers associated with the data from the frame.

9. A method for establishing parallel frame processing, the method comprising:

receiving a plurality of frames at a multi-core processor that operates kernel space and user space contexts of execution;

segmenting frame processing into at least a first stage running in kernel space and a second stage running in user space; and

associating the first and second stages with a point-to-point communication mechanism, wherein the point-to-point communication mechanism allows the first stage and the second stage to exchange data related to the plurality of frames through mutual access to a shared memory.

10. The method according to claim 9, further comprising processing at least two stages in parallel on different frames wherein the at least two stages provide the same processing.

11. The method according to claim 9, wherein at least one of the stages is selected from the group consisting of:

an input stage;

a decryption stage, an application stage, an encryption stage, and an output stage.

12. The method according to claim 9, further comprising processing each stage within an inter-frame arrival period of the frames.

13. The method according to claim 9, wherein the point-to-point communication mechanism is a low latency mechanism.

14. The method according to claim 9, further comprising maintaining substantially consistent frame arrival rates.

15. The method according to claim 14, further comprising extending a processing time of stages with a short processing interval.

16. The method of claim 9, further comprising:

performing the first stage in a first processing core of the multi-core processor; and

performing the second stage in a second processing core of the multi-core processor.

17. The method of claim 9, wherein the point-to-point communication mechanism comprises at least one queue embodied within the shared memory and accessible to both user space and kernel space.

18. The method of claim 17, further comprising:

storing data from the frames in a first queue of the shared memory; and

storing pointers associated with the data from the frames in a second queue of the shared memory.

19. The method of claim 9, further comprising:

accessing the shared memory from the first stage using a first set of pointers; and

accessing the shared memory from the second stage using a second set of pointers.

20. A method for sequentially processing a plurality of frames comprising:

receiving a first frame at a multi-core processor;

placing the first frame in a shared memory of the multi-core processor;

processing by a first processing core of the multi-core processor the first frame according to at least a first processing stage in kernel space during a first time period, the first processing stage accessing data related to the first frame from the shared memory;

receiving a second frame at the multi-core processor;

placing the second frame in the shared memory;

processing by a second processing core of the multi-core processor the first frame according to at least a second processing stage in user space during a second time period that is different than the first time period, the first and second stages exchanging data related to the first frame through mutual access to the shared memory; and

processing by the first processing core of the multi-core processor the second frame according to the first processing stage in kernel space during the second time period, the first processing stage accessing data related to the second frame from the shared memory.

21. The method according to claim 20, wherein the shared memory is accessible from a first context of execution using a first set of pointers and is accessible from a second context of execution using a second set of pointers.