Method and apparatus for efficiently tracking queue entries relative to a timestamp

• US 8,756,350 B2
• Filed: 06/26/2007
• Issued: 06/17/2014
• Est. Priority Date: 06/26/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Blumrich, Matthias A., Chen, Dong, Gara, Alan G., Giampapa, Mark E., Heidelberger, Philip, Ohmacht, Martin, Salapura, Valentina, Vranas, Pavlos
• Primary Examiner(s): RHU, KRIS M
• Application Number:
  US11/768,800
• Publication Number:
  US 20090006672A1
• Time in Patent Office: 2,548 Days
• Field of Search: None
• US Class Current: 710/52
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.

Claims

1. An apparatus for tracking event signals transmitted in a multiprocessor system having a plurality of processor devices, said apparatus comprising:

a queue structure for storing said event signals transmitted in said system;

a logic device associated with said queue structure for controlling enqueuing and dequeuing of received said event signals at said structure; and

,

a counting mechanism for tracking a number of event signals remaining enqueued in said queue structure and dequeued since receipt of a timestamp signal, and, said counting mechanism generating an output signal indicating that all of the event signals present in the queue structure at the time of receipt of said timestamp signal have been dequeued.

2. The apparatus as claimed in claim 1, wherein said queue structure is associated with each of said plurality of processor devices in said multiprocessor system

3. The apparatus as claimed in claim 1, wherein said counting mechanism comprises:

a first counter device responsive to assertion of an enqueue signal and a dequeue signal for counting a number of enqueued event signals in said queue structure; and

,

a second counter device responsive to receipt of said timestamp signal for receiving a count signal representing said number of enqueued event signals in said queue structure, and counting down from said number in response to assertion of each dequeue signal asserted when each said enqueued event signal is dequeued from said queue structure, said second counter device generating said output signal when it counts down to zero.

11. The apparatus as claimed in claim 1, wherein said queue structure is a FIFO structure.

13. The apparatus as claimed in claim 3, wherein said counting mechanism further comprises:

an additional second counter device responsive to receipt of said second timestamp signal for receiving said count signal representing said number of enqueued signals in said queue structure, and counting down from said number in response to assertion of each dequeue signal asserted when each said enqueued event signal is dequeued from said queue structure, said additional second counter device generating a further said output signal when it counts down to zero.

20. The apparatus as claimed in claim 1, wherein new event signals can be added to the queue during the dequeueing of previously received said event signals.

4. An apparatus as claimed in Claim I, wherein said event signals are coherence event signals, and said queue structure is a coherence logic unit associated with each processor of said multiprocessor system.

5. The apparatus as claimed in claim 4, wherein said coherence event signals are transmitted between memory storage devices associated with each respective processor device of said multiprocessor system via a point-to-point signal communication structure architecture.

6. The apparatus as claimed in claim 4, wherein each processor of said multiprocessor system includes an associated cache device, said coherence event signals being broadcast from an issuing processor cache and transmitted in a multiprocessor system to each other processor cache, a coherence event comprising an invalidation request for invalidating a cache line.

7. The apparatus as claimed in claim 4, wherein a sender of event signals in said multiprocessor system includes a DMA logic device, said system coherence logic unit receiving an invalidate request signal from said DMA.

8. The apparatus as claimed in claim 4, wherein said coherence logic unit further comprises:

an arbitration unit responsive to receipt of said generated output signals associated with a respective queue structure for implementing logic to generate an invalidation signal for input to a processor cache.

9. The apparatus as claimed in claim 6, wherein said coherence logic unit further comprises:

one or more snoop filter units to process incoming invalidation requests and present a reduced number of invalidation requests to a processor.

10. The apparatus as claimed in claim 4, wherein said multiprocessor system performs a memory synchronization operation, said coherence logic unit ensuring that all coherence events have been completed by asserting said timestamp signal for input to all queue units in said system, and then waiting until all of the said output signals assert before completing a memory synchronization operation.

12. The apparatus as claimed in claim 4, wherein said counting mechanism is responsive to assertion of a second timestamp signal for tracking a number of events remaining in said queue structure since receipt of said second timestamp signal.

14. A method for tracking event signals transmitted in a multiprocessor system, said method comprising:

intercepting an event signal in said multiprocessor system;

enqueuing and dequeuing intercepted said event signals at a queue structure;

counting a number of event signals enqueued in said queue structure and dequeued from said queue structure since receipt of a timestamp signal;

generating an output signal indicating that all of the event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued;

controlling said enqueuing and dequeuing intercepted said event signals by generating a respective enqueue signal for receipt at said queue structure for controlling input of said intercepted event signal in said queue structure and a dequeue signal for receipt at said queue structure for controlling said dequeuing of said event signal from said queue structure, wherein said counting a number of said event signals enqueued and dequeued from said queue structure includes;

implementing a first counter device responsive to assertion of said enqueue signal and dequeue signal for counting a number of enqueued event signals in said queue structure;

implementing a second counter device responsive to receipt of said timestamp signal for receiving a count signal representing said number of enqueued event signals presently in said queue structure; and

counting down from said number in response to assertion of each dequeue signal asserted when removing said enqueued event signal from said queue structure, said second counter device generating said output signal when it counts down to zero.

15. The method as claimed in claim 14, further comprising:

implementing an additional second counter device responsive to receipt of a second timestamp signal;

responding to assertion of a second timestamp signal for tracking a number of event signals remaining in said queue structure since receipt of said second timestamp signal;

counting a number of event signals enqueued in a respective said queue structure and dequeued from said queue structure since receipt of a second timestamp signal; and

generating second output signal indicating that all of the event signals present in the queue structure at the time of receipt of the second timestamp signal have been dequeued.

21. The method as claimed in claim 14, wherein new event signals can be added to the queue during the dequeueing of previously received said event signals.

16. A queue logic unit for tracking a plurality of event signals in a multiprocessor system, said unit comprising:

a queue structure for storing said coherence event signals transmitted in said system;

a logic device associated with a queue structure for controlling enqueuing and dequeuing of received said event signals at said structure; and

,

a counter mechanism for tracking a number of event signals remaining enqueued in said queue structure and dequeued since receipt of a timestamp signal, and, said counter mechanism generating an output signal indicating that all of the event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued.

17. The queue logic unit as claimed in claim 16, wherein said counting mechanism is further responsive to receipt of said timestamp signal for receiving a count signal representing said number of enqueued event signals in said queue structure, and counting down from said number in response to each dequeue signal asserted when each said enqueued signal is dequeued from said queue structure, said counting mechanism generating said output signal when it counts down to zero.

18. A queue logic unit as claimed in claim 16, wherein said event signals are coherence event signals, and said queue unit is a coherence logic unit associated with each processor of said multiprocessor system.

19. The logic unit as claimed in claim 16, wherein said counting mechanism is responsive to assertion of a second timestamp signal for tracking a number of said events remaining in said queue structure since receipt of said second timestamp signal,

said counter mechanism receiving said count signal representing said number of enqueued event signals in said queue structure, counting down from said number in response to each dequeue signal asserted when each said enqueued event signal is dequeued from said queue structure, and, generating a further output signal when it counts down to zero.