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Controlling DRAM at time DRAM ready to receive command when exiting power down

  • US 8,756,395 B2
  • Filed: 02/27/2012
  • Issued: 06/17/2014
  • Est. Priority Date: 03/10/1998
  • Status: Expired due to Term
First Claim
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1. A method of operation of an integrated circuit controller device that controls a dynamic random access memory (DRAM) device comprising an array of DRAM memory cells, the method comprising:

  • providing a value to the DRAM device, wherein the value represents a time at which the DRAM device is ready to receive a command when exiting from a power down mode, wherein the DRAM device stores the value in a programmable register; and

    providing the command to the DRAM device at the time, wherein the command specifies an access to the array.

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