Controlling DRAM at time DRAM ready to receive command when exiting power down

• US 8,756,395 B2
• Filed: 02/27/2012
• Issued: 06/17/2014
• Est. Priority Date: 03/10/1998
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A., Bystrom, Todd W., May, Bradley A., Davis, Paul G.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US13/406,465
• Publication Number:
  US 20120216059A1
• Time in Patent Office: 841 Days
• Field of Search: 713/300, 713/320, 713/400, 713/401, 713/500, 713/310, 711/167, 711/170, 711/105, 711/154, 365/233.1, 365/226, 365/194
• US Class Current: 711/167
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Claims

1. A method of operation of an integrated circuit controller device that controls a dynamic random access memory (DRAM) device comprising an array of DRAM memory cells, the method comprising:

providing a value to the DRAM device, wherein the value represents a time at which the DRAM device is ready to receive a command when exiting from a power down mode, wherein the DRAM device stores the value in a programmable register; and

providing the command to the DRAM device at the time, wherein the command specifies an access to the array.

2. The method of claim 1, wherein the command specifies activation of a row of the array.

3. The method of claim 1, wherein the command specifies a write operation and the method further comprises:

providing an address of the array, the address being associated with the command that specifies the write operation; and

providing data to the DRAM device, wherein the data is associated with the command that specifies the write operation, wherein the data is to be stored at the address of the array.

4. The method of claim 1, wherein the command specifies a read operation and the method further comprises:

providing an address of the array, the address being associated with the command that specifies the read operation; and

receiving data from the DRAM device, wherein the data is associated with the command that specifies a read operation, wherein the data is stored at the address of the array.

5. The method of claim 1, wherein, while in the power down mode, the DRAM device consumes less power than in a full power mode, and further comprising:

providing the command while the DRAM device is in the full power mode.

6. The method of claim 1, further comprising:

obtaining information from a serial presence detect device; and

generating the value based on the information.

7. The method of claim 6, wherein the information indicates a period of time for an exit from the power down mode, wherein the generating includes dividing the period of time by a period of an external clock signal to select the value in terms of clock cycles of the external clock signal.

8. The method of claim 7, wherein the generating comprises rounding to a next whole number when a fractional number of clock cycles results when dividing the period of time by the period of the external clock signal.

9. The method of claim 1, wherein the providing the value further comprises:

providing first biasing information that is associated with a first period of time during which a delay lock loop circuit of the DRAM device acquires an external clock signal such that a limited functionality of the DRAM device is achieved; and

providing second biasing information that is associated with a second period of time which the delay lock loop circuit acquires the external clock signal such that a full functionality of the DRAM device is achieved.

10. A method of operation of an integrated circuit controller device that controls a DRAM device comprising an array of DRAM memory cells, the method comprising:

outputting, at a first interface of the integrated circuit controller device, a value to the DRAM device, wherein the value represents a period of time during which the DRAM device is not electrically ready to receive a command when exiting from a power down mode, wherein the DRAM device stores the value in a programmable register; and

outputting, at a second interface of the integrated circuit controller device, a command to the DRAM device.

11. The method of claim 10, wherein the period of time occurring immediately following the start of the transition from the power down mode of the DRAM device to a full power mode of the DRAM device.

12. The method of claim 11, wherein, while in the power down mode, the DRAM device consumes less power than in the full power mode, and

wherein the outputting the command occurs while the DRAM device is in the full power mode.

13. The method of claim 10, wherein the command specifies an access to the array.

14. The method of claim 10, wherein the command specifies activation of a row of the array.

15. The method of claim 10, wherein the first interface of the integrated circuit controller device includes a first set of contacts and the second interface of the integrated circuit controller device includes a second set of contacts, wherein the first set of contacts is different than the second set of contacts.

16. The method of claim 10, wherein the integrated circuit controller device is a digital processor.

17. The method of claim 10, wherein outputting the value occurs during an initialization of the DRAM device.

18. A method of operation of an integrated circuit controller device that controls a DRAM device comprising an array of DRAM memory cells, the method comprising:

calculating a value based on information, wherein the value represents a time at which the DRAM device is capable of receiving a command when exiting from a power down mode;

outputting the value to the DRAM device, wherein the DRAM device stores the value in a programmable register; and

providing the command to the DRAM device, wherein the command specifies an access to the DRAM array.

19. The method of claim 18, further comprising:

receiving the information from a serial presence detect device, wherein the information pertains to at least one DRAM device.

20. The method of claim 18, wherein, while in the power down mode, the DRAM device consumes less power than in a full power mode, wherein providing the command occurs while the DRAM device is in the full power mode.

21. The method of claim 18, wherein the information indicates a period of time for an exit from the power down mode, wherein the calculating includes dividing the period of time by a period of an external clock signal to obtain the value in terms of clock cycles of the external clock signal.

22. The method of claim 21, wherein the calculating comprises rounding to a next whole number when a fractional number of clock cycles results when dividing the period of time by the period of the external clock signal.