System for processor power limit management

• US 8,756,442 B2
• Filed: 12/16/2010
• Issued: 06/17/2014
• Est. Priority Date: 12/16/2010
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Naffziger, Samuel D., Petry, John P., Bondalapati, Kiran, Hughes, William A.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Choudhury, Zahid
• Application Number:
  US12/970,172
• Publication Number:
  US 20120159198A1
• Time in Patent Office: 1,279 Days
• Field of Search: 713/300, 713/310, 713/320, 713/322, 713/323
• US Class Current: 713/300
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a power dissipation due to processor load. A power controller is configured to adjust a processor power parameter based on the power target and the power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the power dissipation stays below the processor power target, software processor power target and the agent processor power target.

Claims

1. A processor comprising:

a first programmable location configured to store a processor power target;

a power monitor configured to estimate a power dissipation due to processor load;

a power controller configured to adjust a processor power parameter based on the power target and the power dissipation;

comprising an interface for an operating system, wherein a second programmable location is configured to store a software processor power target accessible by the operating system; and

a sideband interface for an external agent, wherein a third programmable location is configured to store an agent processor power target accessible by the external agent;

wherein the processor power target is set to the lowest value stored in the first and second programmable locations.

2. The processor of claim 1 wherein the processor power target is set to the lowest value stored in the first, second and third programmable locations.

3. The processor of claim 1 wherein the monitor is configured to estimate a power dissipation from loading associated with multiple cores of the processor.

4. The processor of claim 1 wherein the power controller is configured to adjust a processor power parameter associated with multiple cores of the processor.

5. The processor of claim 1 wherein the power controller is configured to adjust a processor core voltage such that the power dissipation stays below the power target.

6. The processor of claim 1 wherein the power controller is configured to adjust a processor core frequency such that the power dissipation stays below the power target.

7. The processor of claim 1 wherein the power monitor is configured to estimate the power dissipation during a time window by tracking processor instructions, each processor instruction having a power consumption estimation and calculating the power dissipation from the power consumption estimates from the power instructions tracked during the time window.

8. A method of limiting power dissipation in a processor, the method comprising:

storing a processor power target in a first programmable location;

estimating a power dissipation due to processor load;

adjusting a processor power parameter based on the power target and the power dissipation;

providing an interface for an operating system, wherein a second programmable location is configured to store a software processor power target accessible by the operating system; and

providing a sideband interface for an external agent, wherein a third programmable location is configured to store an agent processor power target accessible by the external agent;

wherein the processor power target is set to the lowest value stored in the first and second programmable locations.

9. The method of claim 8 wherein the processor power target is set to the lowest value stored in the first, second and third programmable locations.

10. The method of claim 8 further comprising estimating a power dissipation from loading associated with multiple cores of the processor.

11. The method of claim 8 further comprising adjusting a processor power parameter associated with multiple cores of the processor.

12. The method of claim 8 further comprising adjusting a processor core voltage such that the power dissipation stays below the power target.

13. The method of claim 8 further comprising adjusting a processor core frequency such that the power dissipation stays below the power target.

14. The method of claim 8 further comprising estimating the power dissipation during a time window.

15. A non-transitory computer readable media including hardware design code stored thereon, and when processed generates other intermediary data to create mask works for a processor that is configured to perform a method of limiting power dissipation in a processor, the method comprising:

storing a processor power target in a first programmable location;

estimating a power dissipation due to processor load;

adjusting a processor power parameter based on the power target and the power dissipation;

providing an interface for an operating system, wherein a second programmable location is configured to store a software processor power target accessible by the operating system; and

providing a sideband interface for an external agent, wherein a third programmable location is configured to store an agent processor power target accessible by the external agent;

wherein the processor power target is set to the lowest value stored in (1) the first and second programmable locations or (2) the first, second and third programmable locations.