Microprocessor having a low-power mode and a non-low power mode, data processing system and computer program product

• US 8,756,446 B2
• Filed: 04/11/2008
• Issued: 06/17/2014
• Est. Priority Date: 04/11/2008
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rancurel, Vianney, Bufferne, Vincent, Meunier, Gregory
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US12/933,229
• Publication Number:
  US 20110035613A1
• Time in Patent Office: 2,258 Days
• Field of Search: 713/322, 713/323, 713/400, 713500-503, 713/600
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number.

Claims

1. A microprocessor having a low power mode and a non-low power mode, said microprocessor comprising:

a processor core for executing instructions provided to said microprocessor;

a clock driver for a clock providing a clock signal which in said non-low power mode has a first frequency and in said low power mode has a second frequency lower than said first frequency;

a hardware timer connected to the clock driver, the hardware timer for scheduling an execution of an event by said microprocessor at a future point in time, and to store a first counter value representing a remaining period of time between a current point in time and the future point in time as a number of clock cycles of said clock signal at the first frequency; and

a timer controller for storing, in response to said microprocessor switching from said non-low power mode to said low power mode after the hardware timer is started, a second counter value that is a second number of clock cycles at the first frequency from a start point to the current point of time, calculating, in response to said microprocessor switching from said non-low power mode to said low power mode after the hardware timer is started, a third counter value based on the first and second counter values, the third counter value is a number of clock cycles of the clock signal at said second frequency that corresponds to the remaining period of time represented by the number of clock cycles of the clock signal at the first frequency, and storing the third counter value to represent the remaining period of time between the current point of time and the future point in time as the number of clock cycles of the clock signal at the second frequency, wherein the hardware timer is set to expire at the future point in time in response to the third counter value of the hardware timer.

2. The microprocessor as claimed in claim 1, wherein the timer controller to calculate a fourth counter value based on the second and third counter values, wherein the fourth counter value is the third number of clock cycles of the clock signal at said second frequency that corresponds to the same number of clock cycles of the clock signal at the first frequency;

and to calculate an adjusted counter value based on the first, second, third, and fourth counter values, the adjusted counter value to represent the remaining period of time between when the microprocessor switches from the low power mode to the non-low power mode and the future point in time, wherein the hardware timer is set to expire at the future point in time in response to the adjusted value of the hardware timer.

3. A microprocessor as claimed in claim 2, wherein said hardware timer includes a counter connected to said clock for counting a counted number of clock cycles of said clock signal.

4. A microprocessor as claimed in claim 3, wherein said timer controller includes a converter for adjusting a counter value of said counter and/or an expiry time to which said hardware timer is set based on said number of clock cycles of said clock during said low power mode period.

5. A data processing system comprising:

a microprocessor as claimed in claim 3;

a memory including data representing instructions executable by said microprocessor, said instructions including timer control instructions for determining, when said microprocessor switches from said non-low power mode to said low power mode after the hardware timer is started, a number of clock cycles of the clock signal at said second frequency that corresponds to the remaining period of time represented by the number of clock cycles of the clock signal at the first frequency, and adjusting the value in said hardware timer to represent the remaining period of time between the current point of time and the future point in time as the number of clock cycles of the clock signal at the second frequency, wherein the hardware timer is set to expire at the future point in time in response to the adjusted value of the hardware timer.

6. A data processing system as claimed in claim 5, wherein said instructions include a set of instructions representing an operating system, said operating system forming an interface between said microprocessor and applications running on said microprocessor;

said set including said timer control instructions.

7. A microprocessor as claimed in claim 2, wherein said timer controller includes a converter for adjusting a counter value of said counter and/or an expiry time to which said hardware timer is set based on said number of clock cycles of said clock during said low power mode period.

8. A data processing system comprising:

a microprocessor as claimed in claim 7;

a memory including data representing instructions executable by said microprocessor, said instructions including timer control instructions for determining, when said microprocessor switches from said non-low power mode to said low power mode, a number of clock cycles of the clock signal at said second frequency that corresponds to the remaining period of time represented by the number of clock cycles of the clock signal at the first frequency, and adjusting the value in said hardware timer to represent the remaining period of time between the current point of time and the future point in time as the number of clock cycles of the clock signal at the second frequency, wherein the hardware timer is set to expire at the future point in time in response to the adjusted value of the hardware timer.

9. A data processing system as claimed in claim 8, wherein said instructions include a set of instructions representing an operating system, said operating system forming an interface between said microprocessor and applications running on said microprocessor;

said set including said timer control instructions.

10. A data processing system comprising:

a microprocessor as claimed in claim 2;

a memory including data representing instructions executable by said microprocessor, said instructions including timer control instructions for determining, when said microprocessor switches from said non-low power mode to said low power mode after the hardware timer is started, a number of clock cycles of the clock signal at said second frequency that corresponds to the remaining period of time of the number of clock cycles represented by the clock signal at the first frequency, and adjusting the value in said hardware timer to represent the remaining period of time between the current point of time and the future point in time as the number of clock cycles of the clock signal at the second frequency, wherein the hardware timer is set to expire at the future point in time in response to the adjusted value of the hardware timer.

11. A data processing system as claimed in claim 2, wherein said instructions include a set of instructions representing an operating system, said operating system forming an interface between said microprocessor and applications running on said microprocessor;

said set including said timer control instructions.

12. A microprocessor having a low power mode and a non-low power mode, said microprocessor comprising:

a clock driver for clock to provide a clock signal which has a first frequency when the microprocessor is in the non-low power mode and has a second frequency lower than the first frequency when the microprocessor is in the low power mode;

a hardware timer being connected to the clock, the hardware timer for scheduling an execution of an event by said microprocessor at a future point in time, and to store a first counter value representing a remaining period of time between a current point in time and the future point in time as a number of clock cycles of said clock signal at the first frequency; and

a timer controller for storing, in response to said microprocessor switching from said non-low power mode to said low power mode after the hardware timer is started, a second counter value that is a second number of clock cycles at the first frequency from a start point to the current point of time, calculating, in response to said microprocessor switching from said non-low power mode to said low power mode after the hardware timer is started, a third counter value based on the first and second counter values, the third counter value is a number of clock cycles of the clock signal at said second frequency that corresponds to the remaining period of time represented by the number of clock cycles of the clock signal at the first frequency, and storing the third counter value to represent the remaining period of time between the current point of time and the future point in time as the number of clock cycles of the clock signal at the second frequency, wherein the hardware timer is set to expire at the future point in time in response to the third counter value of the hardware timer.

13. The microprocessor as claimed in claim 12, wherein the timer controller to calculate a fourth counter value based on the second and third counter values, wherein the fourth counter value is the third number of clock cycles of the clock signal at said second frequency that corresponds to the same number of clock cycles of the clock signal at the first frequency;

and to calculate an adjusted counter value based on the first, second, third, and fourth counter values, the adjusted counter value to represent the remaining period of time between when the microprocessor switches from the low power mode to the non-low power mode and the future point in time, wherein the hardware timer is set to expire at the future point in time in response to the adjusted value of the hardware timer.

14. The microprocessor of claim 13, wherein the hardware timer includes a counter connected to the clock, the counter to count a counted number of clock cycles of the clock signal.

15. The microprocessor of claim 14, wherein the timer controller includes a converter to adjust a counter value of the counter and/or an expiry time to which the hardware timer is set based on the number of clock cycles of the clock during the low power mode period.

16. The microprocessor of claim 13, wherein the timer controller includes a converter to adjust a counter value of the counter and/or an expiry time to which the hardware timer is set based on the number of clock cycles of the clock during the low power mode period.

17. A method comprising:

producing a clock signal which has a first frequency when a microprocessor is in a non-low power mode, and which has a second frequency lower than the first frequency when the microprocessor is in a low power mode;

scheduling, by a hardware timer, an execution of an event by the microprocessor at a future point in time;

determining a period of time between a start point in time and the future point in time of the event based on a number of clock cycles of the clock signal at the first frequency;

storing the number of clock cycles in the period of time as a first counter value;

storing a second counter value in response to the microprocessor being switched from the non-low power mode to the low power mode, wherein the second counter value is a second number of clock cycles at the first frequency from the start point;

storing a third counter value in response to the microprocessor being switched from the low power mode to the non-low power mode, wherein the third counter value is a third number of clock cycles at the second frequency while the microprocessor was in the low power mode;

calculating a fourth counter value based on the second and third counter values, wherein the fourth counter value is the third number of clock cycles of the clock signal at said second frequency that corresponds to the same number of clock cycles of the clock signal at the first frequency; and

calculating an adjusted counter value based on the first, second, third, and fourth counter values, the adjusted counter value to represent the remaining period of time between when the microprocessor switches from the low power mode to the non-low power mode and the future point in time, wherein the hardware timer is set to expire at the future point in time in response to the adjusted value of the hardware timer.

18. The method of claim 17, further comprising:

counting, by a counter of the hardware timer, a counted number of clock cycles of the clock signal.

19. The method of claim 17, further comprising:

adjusting, by a converter of the timer controller, a counter value of the counter and/or an expiry time to which the hardware timer is set based on the number of clock cycles of the clock during the low power mode period.

20. The method of claim 17, further comprising:

adjusting a stored value to an adjusted value the determined number of clock cycles;

comparing a value of the hardware timer to the adjusted value; and

determining that the hardware timer has expired when the value of the hardware timer matches the adjusted value.