Method and apparatus for evaluating and optimizing a signaling system

• US 8,756,469 B2
• Filed: 06/12/2013
• Issued: 06/17/2014
• Est. Priority Date: 02/02/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared, Chau, Pak Shing, Stonecypher, William Franklin
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US13/915,879
• Publication Number:
  US 20130272360A1
• Time in Patent Office: 370 Days
• US Class Current: 714/745
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/31717 Interconnect testing by scan techniques see G01R31/31855
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/31855 Interconnection testing, e.g. crosstalk, shortcircuits
• CPC Class Codes: G01R 31/318577 AC testing, e.g. current testing, burn-in
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: H04B 1/04 Circuits
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/242 : by comparing a transmitted test signal with a locally generated replica
• CPC Class Codes: H04L 1/243 : at the transmitter, using a loop-back
• CPC Class Codes: H04L 1/244 : test sequence generators
• CPC Class Codes: H04L 25/03885 : adaptive
• CPC Class Codes: H04L 5/1438 : Negotiation of transmission parameters prior to communication modified according to link quality H04L1/0001

Abstract

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Claims

1. An integrated circuit, comprising:

circuitry to generate a repeating pattern signal during a test mode; and

circuitry to serially transmit a signal to a receiver, the signal comprising a data signal during a normal mode and the repeating pattern signal during the test mode, where the circuitry is to serially transmit the repeating pattern signal to the receiver during the test mode using alternate values of at least one transmission parameter affecting proper reception of the repeating pattern signal by the receiver; and

where the integrated circuit is during the normal mode to apply an operating value for the at least one parameter to transmit the data signal, the operating value selected in dependence on the evaluation of the repeating pattern signal serially transmitted during the test mode as received by the receiver.

2. The integrated circuit of claim 1, where the at least one transmission parameter includes at least one of a timing parameter or a voltage parameter influencing ability to distinguish logic levels of the data signal at the receiver.

3. The integrated circuit of claim 1, where the at least one transmission parameter comprises a timing offset relative to a timing reference, the timing offset used by the circuitry to serially transmit the signal to the receiver.

4. The integrated circuit of claim 3, where the circuitry to transmit is to adjust a setting for the timing offset over a range of values to determine a specific value of the timing offset to be applied as the operating value.

5. The integrated circuit of claim 1, where the integrated circuit further comprises a shift register to store digital values transmitted as part of the data signal and to store elements of the repeating pattern signal during the test mode, and where the repeating pattern signal has a data length greater than a number of shift elements of the shift register.

6. The integrated circuit of claim 5, where the shift register is a linear feedback shift register.

7. The integrated circuit of claim 6, where the linear feedback shift register is to generate the repeating pattern signal during the test mode.

8. The integrated circuit of claim 1, where the transmitter is to serially transmit the repeating pattern signal to the receiver over a differential conductor and where the circuitry to serially transmit comprises a differential path transmitter.

9. The integrated circuit of claim 1, where the integrated circuit is to enter the test mode at startup of a system comprising the integrated circuit.

10. A method of evaluating a value of at least one parameter used by a transmitter in an integrated circuit, the parameter affecting serial transmission of a signal to a receiver, the method comprising:

generating a repeating pattern signal during a test mode;

serially transmitting the signal to the receiver, where the signal comprises a data signal during a normal mode and the repeating pattern signal during the test mode;

during a first iteration of serially transmitting the repeating pattern signal during the test mode, using a first value of the at least one parameter;

during a second iteration of serially transmitting the repeating pattern signal during the test mode, using a second value of the at least one parameter, the first and second values being alternate values of the at least one parameter, such that in the respective iterations, the repeating pattern signal is serially transmitted using the alternate values of the at least one parameter;

selecting an operating value for the at least one parameter to transmit the data signal in dependence on the evaluation of the repeating pattern signal serially transmitted during the test mode as received by the receiver; and

applying the operating value within the integrated circuit during the normal mode to serially transmit the data signal to the receiver.

11. The method of claim 10, where the at least one parameter includes at least one of a timing parameter of the transmitter or a voltage parameter influencing ability to distinguish logic levels of the data signal at the receiver.

12. The method of claim 10, where the at least one parameter comprises a timing offset relative to a timing reference for use in serially transmitting the data signal.

13. The method of claim 10, where serially transmitting comprises using a shift register to store digital values transmitted as part of the data signal, and to store elements of the repeating pattern signal during the test mode, and where the repeating pattern signal has a data length greater than a number of shift elements of the shift register.

14. The method of claim 10, where generating includes using a linear feedback shift register to generate the repeating pattern signal during the test mode.

15. The method of claim 10, where serially transmitting comprises serially transmitting the repeating pattern signal as a differential signal to the receiver over a differential conductor.

16. The method of claim 10, further comprising entering the test mode at startup of a system comprising the integrated circuit.

17. The method of claim 10, where the at least one parameter comprises an output drive level for use in serially transmitting the data signal.

18. The method of claim 10, further comprising, sweeping the parameter through a range of values in multiple iterations of transmitting the repeating pattern signal during the test mode, the range of values including the alternate values, and responsively selecting a specific operating value for the at least one parameter to serially transmit the data signal during the normal mode.

19. An integrated circuit to connect to a receiver via an electrical conductor coupling the integrated circuit and the receiver, the integrated circuit comprising:

circuitry to generate a repeating pattern signal during a test mode; and

circuitry to serially and differentially transmit a signal to the receiver via the electrical conductor, the signal comprising a data signal during a normal mode and the repeating pattern signal during the test mode, using in a first iteration a first value of at least two alternate values of a transmission parameter to transmit the repeating pattern signal during the test mode, the parameter affecting proper reception of the signal at the receiver, and using in a second iteration a second value of the at least two alternate values of the parameter to transmit the repeating pattern signal during the test mode, such that the repeating pattern signal is serially and differentially transmitted using alternate values of the at least one parameter; and

where the integrated circuit is to apply a specific value of the at least one parameter for use in serially and differentially transmitting the data signal during the normal operating mode, responsive to receipt at the receiver of the repeating pattern signal transmitted using the alternate values;

where the at least one parameter includes at least one of a timing parameter a voltage parameter or an output drive level influencing ability to distinguish logic levels of the data signal at the receiver.

20. The integrated circuit of claim 19, where the integrated circuit further comprises a linear feedback shift register to generate the repeating pattern signal during the test mode, a data length of the pattern that repeats as the repeating pattern signal being greater than a number of shift elements in the linear feedback shift register.