Modifying a target system configuration to utilize a different synchronization module for performing synchronization among multiple programmable hardware elements

• US 8,756,565 B2
• Filed: 06/19/2012
• Issued: 06/17/2014
• Est. Priority Date: 02/17/2012
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Graf, Christopher F., Brown, Ryan H., Baker, Daniel J., DeVoe, Matthew J.
• Primary Examiner(s): Das, Chameli
• Application Number:
  US13/527,208
• Publication Number:
  US 20130219356A1
• Time in Patent Office: 728 Days
• Field of Search: None
• US Class Current: 717/110
• CPC Class Codes: G05B 19/05 Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
• CPC Class Codes: G06F 11/3696 Methods or tools to render software testable
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management

Abstract

Customizing a target system. The target system may include a first device with a first programmable hardware element (PHE) and a second device with a second PHE. Synchronization modules may be provided for implementation on the first and second PHEs. The synchronization modules may provide a standard interface for interacting with other code. A user may specify user-created code for the first and second PHEs which utilizes the synchronization modules. The user-created code may interact with the synchronization modules using the standard interface. Accordingly, hardware descriptions may be generated for the first and second PHEs of the target system. Different modules may be used for different interconnects. Additionally, multiple synchronization modules may be used, e.g., dynamically, during operation of the target system.

Claims

1. A method for modifying a program for a target system, wherein the target system comprises a first device with a first programmable hardware element (PHE), comprising:

storing a first program for implementation on the first PHE of the first device, wherein the first program comprises;

1) a first synchronization module having code for implementation on the first PHE of the first device, wherein the first synchronization module provides a standard interface for interacting with other code; and

2) first user-created code which performs a first function;

wherein the first synchronization module is configured to adjust timing of the first user-created code in the first program;

wherein the first synchronization module is configured to utilize a first interconnect of a first type;

receiving user input to modify the first synchronization module to utilize a second interconnect of a second different type; and

modifying the first synchronization module in response to the user input, wherein said modifying the first synchronization module to utilize a second interconnect of a second different type does not change the standard interface of the first synchronization module, wherein the first user-created code does not require modification in response to said modifying the first synchronization module to utilize the second interconnect of the second different type, wherein said modifying the first synchronization module comprises;

modifying the first program to replace the first synchronization module with a second synchronization module that supports the second interconnect of the second different type, wherein the second synchronization module uses the standard interface and the first user-created code does not require modification in response to using the second synchronization module.

2. The method of claim 1, wherein the target system comprises a second device having a second PHE, wherein the method further comprises:

storing a second program for implementation on the second PHE of the second device, wherein the second program comprises;

1) a third synchronization module having code for implementation on the second PHE of the second device, wherein the third synchronization module provides the standard interface for interacting with other code; and

2) second user-created code which performs a second function;

wherein the third synchronization module is configured to adjust timing of the second user-created code in the second program;

wherein the third synchronization module is configured to utilize the first interconnect of the first type;

receiving user input modifying the third synchronization module to utilize the second interconnect of the second different type.

3. The method of claim 1, further comprising:

generating a hardware description for the first PHE based on the modified first synchronization module and the first user-created code; and

configuring the first PHE according to the hardware description, wherein during operation, the first PHE is configured to adjust timing of the first user-created code using the second interconnect according to the modified first synchronization module.

4. The method of claim 1, wherein said modifying is performed automatically in response to the user input.

5. The method of claim 1, wherein the first program comprises a graphical program, the graphical program comprising a plurality of interconnected nodes that visually indicates the functionality of the graphical program.

6. The method of claim 1, wherein the first user-created code utilizes a plurality of custom triggers, wherein each custom trigger is invoked or received using the first synchronization module.

7. The method of claim 1, further comprising:

receiving user input selecting the first synchronization module from a library of synchronization modules.

8. The method of claim 1, further comprising:

receiving user input specifying the first synchronization module and the first user-created code.

9. The method of claim 1, wherein the first interconnect or the second interconnect comprise one of:

a simple digital interface;

Ethernet;

wireless communication;

or

an optical link.

10. A non-transitory, computer accessible memory medium storing program instructions for modifying a program for a target system, wherein the target system comprises a first programmable hardware element (PHE), wherein the program instructions are executable to:

display a first program for implementation on the first PHE, wherein the first program comprises;

1) a first synchronization module having code for implementation on the first PHE, wherein the first synchronization module provides a standard interface for interacting with other code; and

2) first user-created code which performs a first function;

wherein the first synchronization module is configured to synchronize timing of the first user-created code in the first program, wherein the first synchronization module is configured to utilize a first interconnect of a first type;

receive user input to replace the first synchronization module with a second synchronization module to utilize a second interconnect of a second different type; and

replace the first synchronization module with the second synchronization module in response to the user input, wherein the second synchronization module also provides the standard interface for interacting with other code, wherein to utilize the second interconnect of the second different type, the second synchronization module does not change the standard interface, and wherein the first user-created code does not require modification in response to said replacing the first synchronization module with the second synchronization module.

11. The non-transitory, computer accessible memory medium of claim 10, wherein the target system comprises a second PHE, wherein the program instructions are further executable to:

display a second program for implementation on the second PHE, wherein the second program comprises;

1) a third synchronization module having code for implementation on the second PHE, wherein the third synchronization module provides the standard interface for interacting with other code; and

2) second user-created code which performs a second function;

wherein the third synchronization module is configured to synchronize timing of the second user-created code in the second program with the first user-created code in the first program, wherein the third synchronization module is configured to utilize the first interconnect of the first type;

receive user input to replace the third synchronization module with a fourth synchronization module to utilize the second interconnect of the second different type; and

replace the third synchronization module with the fourth synchronization module in response to the user input, wherein the fourth synchronization module also provides the standard interface for interacting with other code, and wherein the second user-created code does not require modification in response to said receiving user input replacing the third synchronization module with the fourth synchronization module.

12. The non-transitory, computer accessible memory medium of claim 10, wherein the target system comprises a second PHE, wherein the program instructions are further executable to:

display a second program for implementation on the second PHE, wherein the second program comprises;

1) a third synchronization module having code for implementation on the second PHE, wherein the third synchronization module provides the standard interface for interacting with other code; and

2) second user-created code which performs a second function;

wherein the third synchronization module is configured to synchronize timing of the second user-created code in the second program with the first user-created code in the first program, wherein the third synchronization module is configured to utilize the first interconnect of the first type;

in response to receiving user input to replace the first synchronization module with the second synchronization module, automatically replace the third with a fourth synchronization module to utilize the second interconnect of the second different type, wherein the fourth synchronization module also provides the standard interface for interacting with other code, and wherein the second user-created code does not require modification in response to said replacing the third synchronization module with the fourth synchronization module.

13. The non-transitory, computer accessible memory medium of claim 10, wherein said replacing is performed automatically in response to the user input.

14. The non-transitory, computer accessible memory medium of claim 10, wherein the program instructions are further executable to:

generate a hardware description for the first PHE based on the second synchronization module and the first user-created code.

15. The non-transitory, computer accessible memory medium of claim 14, wherein the program instructions are further executable to:

configure the first PHE according to the hardware description, wherein during operation, the first PHE is configured to adjust timing of the first user-created code using the second interconnect according to the modified first synchronization module.

16. The non-transitory, computer accessible memory medium of claim 10, wherein the first program comprises a graphical program, the graphical program comprising a plurality of interconnected nodes that visually indicates the functionality of the graphical program.

17. The non-transitory, computer accessible memory medium of claim 10, wherein the first user-created code utilizes a plurality of custom triggers, wherein each custom trigger is invoked or received using the first synchronization module.

18. The non-transitory, computer accessible memory medium of claim 10, wherein the program instructions are further executable to:

receive user input selecting the first synchronization module from a library of synchronization modules;

wherein said receiving user input to replace the first synchronization module with the second synchronization module comprises receiving user input selecting the second synchronization module from the library of synchronization modules.

19. The non-transitory, computer accessible memory medium of claim 10, wherein the first interconnect or the second interconnect comprise one of:

a simple digital interface;

Ethernet;

wireless communication;

or

an optical link.