Configurable interposer

• US 8,759,152 B2
• Filed: 06/06/2012
• Issued: 06/24/2014
• Est. Priority Date: 11/16/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gluschenkov, Oleg, Song, Yunsheng, Ting, Tso-Hui, Wang, Ping-Chuan
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US13/489,596
• Publication Number:
  US 20120241977A1
• Time in Patent Office: 748 Days
• Field of Search: None
• US Class Current: 438/109
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0286 : Programmable, customizable or modifiable circuits by programmable non-printed jumper connections H05K3/222
• CPC Class Codes: H05K 1/142 : Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
• CPC Class Codes: H05K 2201/2018 : Presence of a frame in a printed circuit or printed circuit assembly
• CPC Class Codes: H05K 2203/1572 : Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing

Abstract

A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV'"'"'s) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers.

Claims

1. A method of forming a semiconductor structure comprising:

forming an array of interposer units by selecting each interposer unit in said array from a set of at least two interposer units, wherein each of said at least two interposer units is configured to fit into a same space in said array and provide different configurations in electrical connections therethrough, and each interposer unit in said array is held at a fixed position relative to other interposer units within said array without being attached to any structure at a time of formation of said array of interposer units; and

bringing each of a first semiconductor chip and a second semiconductor chip in physical contact with, and attaching said first semiconductor chip and a second semiconductor chip to, said array of interposer units after formation of said array of interposer units and while each interposer unit in said array is held at said fixed position relative to other interposer units within said array.

2. The method of claim 1, further comprising testing at least one of said first semiconductor chip and said second semiconductor chip prior to forming said array, wherein data from said testing is employed to select said interposer unit from said at least two interposer units.

3. The method of claim 1, further comprising forming a molding compound structure between said first and second semiconductor chips, wherein said molding compound structure and said first and second semiconductor chips encapsulate said array of interposer units.

4. The method of claim 1, further comprising forming a plurality of interposer units, wherein each interposer unit among said plurality of interposer units includes a through-substrate via (TSV) structure embedded in an interposer substrate, an upper contact pad located on one side of said interposer substrate, and a lower contact pad located on another side of said interposer substrate, wherein said array of interposer units includes interposer units that are selected from said plurality of interposer units.

5. The method of claim 1, further comprising employing an interposer-frame means to hold each interposer unit in said array of interposer units in a fixed position relative to other interposer units in said array while said array of interposer units is bonded to said first and second semiconductor chips.

6. A method of forming an array of interposer units, said method comprising:

forming a plurality of through-substrate via (TSV) structures in a substrate;

forming a plurality of conductive metal lines contacting a TSV structure on one side of said substrate;

dicing said substrate to form a plurality of interposer units; and

placing some of said plurality of interposer units in proximity to one another to form an array of interposer units, wherein each interposer unit in said array is placed at a fixed position relative to other interposer units within said array without attaching any interposer unit in said array to any structure at a time of formation of said array of interposer units.

7. The method of claim 6, wherein said array of interposer units is formed by selecting an interposer unit in said array from a set of at least two interposer units, wherein each of said at least two interposer units is configured to fit into a same space in said array and provide different configurations in electrical connections therethrough.

8. The method of claim 6, further comprising employing an interposer-frame means to hold each interposer unit in said array of interposer units in a fixed position relative to other interposer units in said array.

9. The method of claim 6, further comprising holding each interposer unit in said plurality of interposer units in a fixed position relative to other interposer units employing interposer-frame means.

10. The method of claim 6, further comprising forming another plurality of conductive metal lines contacting a TSV structure on another side of said substrate before dicing said substrate.