Semiconductor device and method for manufacturing the same

• US 8,759,167 B2
• Filed: 11/29/2012
• Issued: 06/24/2014
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Akimoto, Kengo, Sasaki, Toshinari
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US13/688,598
• Publication Number:
  US 20130089950A1
• Time in Patent Office: 572 Days
• Field of Search: 438/104, 438151-156, 257/E21.046, 257/29.101, 257/27.121
• US Class Current: 438/151
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate insulating film over a gate electrode;

forming a first non-single crystalline oxide semiconductor film comprising indium by sputtering over the gate electrode with the gate insulating film interposed therebetween;

forming a second non-single crystalline oxide semiconductor film comprising indium by sputtering over the first non-single crystalline oxide semiconductor film, the second non-single crystalline oxide semiconductor film having a lower electrical conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming a conductive layer over the second oxide semiconductor layer;

etching the conductive layer to form a source electrode and a drain electrode, wherein part of the second oxide semiconductor layer between the source electrode and the drain electrode is etched so that a thickness of the second oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second oxide semiconductor layer below the source electrode and the drain electrode; and

forming an insulating film comprising silicon over the second oxide semiconductor layer, the source electrode and the drain electrode, wherein an upper surface of the second oxide semiconductor layer between the source electrode and the drain electrode contacts the insulating film.

8. The method according to claim 1, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

17. The method according to claim 1, wherein the first non-single crystalline oxide semiconductor film comprises crystal grains in an amorphous structure.

23. The method according to claim 1, further comprising a step of forming a first n-type conductivity region between the source electrode and the second oxide semiconductor layer and a second n-type conductivity region between the drain electrode and the second oxide semiconductor layer.

25. The method according to claim 1, wherein a thickness of the first non-single crystalline oxide semiconductor film is 1 to 50 nm.

27. The method according to claim 1, wherein a thickness of the second non-single crystalline oxide semiconductor film is 10 to 300 nm.

29. The method according to claim 1, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second oxide semiconductor layer.

36. The method according to claim 1, wherein the first oxide semiconductor layer is thinner than the second oxide semiconductor layer.

38. The method according to claim 1, wherein the second oxide semiconductor layer has a carrier concentration lower than 1×

10¹⁷/cm³.

40. The method according to claim 1, wherein the first oxide semiconductor layer has a electrical conductivity higher than 1×

10<sup>−

3</sup> S/cm.

2. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate insulating film over a gate electrode;

forming a first non-single crystalline oxide semiconductor film comprising indium by sputtering over the gate electrode with the gate insulating film interposed therebetween;

forming a second non-single crystalline oxide semiconductor film comprising indium by sputtering over the first non-single crystalline oxide semiconductor film, the second non-single crystalline oxide semiconductor film having a lower electrical conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming a conductive layer over the second oxide semiconductor layer;

etching the conductive layer to form a source electrode and a drain electrode, wherein part of the second oxide semiconductor layer between the source electrode and the drain electrode is etched so that a thickness of the second oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second oxide semiconductor layer below the source electrode and the drain electrode; and

forming a protective film comprising silicon over the second oxide semiconductor layer, the source electrode and the drain electrode, wherein an upper surface of the second oxide semiconductor layer between the source electrode and the drain electrode contacts the protective film.

9. The method according to claim 2, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

18. The method according to claim 2, wherein the first non-single crystalline oxide semiconductor film comprises crystal grains in an amorphous structure.

26. The method according to claim 2, wherein a thickness of the first non-single crystalline oxide semiconductor film is 1 to 50 nm.

28. The method according to claim 2, wherein a thickness of the second non-single crystalline oxide semiconductor film is 10 to 300 nm.

30. The method according to claim 2, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second oxide semiconductor layer.

37. The method according to claim 2, wherein the first oxide semiconductor layer is thinner than the second oxide semiconductor layer.

39. The method according to claim 2, wherein the second oxide semiconductor layer has a carrier concentration lower than 1×

10¹⁷/cm³.

41. The method according to claim 2, wherein the first oxide semiconductor layer has a electrical conductivity higher than 1×

10<sup>−

3</sup> S/cm.

3. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate insulating film over a gate electrode;

forming a first non-single crystalline oxide semiconductor film comprising indium, gallium and zinc by sputtering over the gate electrode with the gate insulating film interposed therebetween, the first non-single crystalline oxide semiconductor film comprising crystal grains in an amorphous structure;

forming a second non-single crystalline oxide semiconductor film comprising indium, gallium and zinc by sputtering over the first non-single crystalline oxide semiconductor film, the second non-single crystalline oxide semiconductor film having a lower electrical conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming a conductive layer over the second oxide semiconductor layer;

etching the conductive layer to form a source electrode and a drain electrode, wherein part of the second oxide semiconductor layer between the source electrode and the drain electrode is etched so that a thickness of the second oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second oxide semiconductor layer below the source electrode and the drain electrode; and

forming an insulating film comprising silicon over the second oxide semiconductor layer, the source electrode and the drain electrode.

12. The method according to claim 3, wherein the insulating film is in contact with an upper surface of the second oxide semiconductor layer between the source electrode and the drain electrode.

16. The method according to claim 3, wherein a grain size of the crystal grains of the first non-single crystalline oxide semiconductor film is not larger than 10 nm.

31. The method according to claim 3, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second oxide semiconductor layer.

4. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate insulating film over a gate electrode;

forming a first non-single crystalline oxide semiconductor film comprising indium by sputtering over the gate electrode with the gate insulating film interposed therebetween;

forming a second non-single crystalline oxide semiconductor film comprising indium by sputtering over the first non-single crystalline oxide semiconductor film successively after forming the first non-single crystalline oxide semiconductor film without exposing the first non-single crystalline oxide semiconductor film to air, the second non-single crystalline oxide semiconductor film having a lower electrical conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming a conductive layer over the second oxide semiconductor layer;

etching the conductive layer to form a source electrode and a drain electrode, wherein part of the second oxide semiconductor layer between the source electrode and the drain electrode is etched so that a thickness of the second oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second oxide semiconductor layer below the source electrode and the drain electrode; and

forming an insulating film comprising silicon over the second oxide semiconductor layer, the source electrode and the drain electrode.

10. The method according to claim 4, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

13. The method according to claim 4, wherein the insulating film is in contact with an upper surface of the second oxide semiconductor layer between the source electrode and the drain electrode.

19. The method according to claim 4, wherein the first non-single crystalline oxide semiconductor film comprises crystal grains in an amorphous structure.

24. The method according to claim 4, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film is formed by pulsed DC sputtering.

32. The method according to claim 4, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second oxide semiconductor layer.

5. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate insulating film over a gate electrode;

forming a first non-single crystalline oxide semiconductor film comprising indium, gallium and zinc by DC sputtering over the gate electrode with the gate insulating film interposed therebetween;

forming a second non-single crystalline oxide semiconductor film comprising indium, gallium and zinc by DC sputtering over the first non-single crystalline oxide semiconductor film, the second non-single crystalline oxide semiconductor film having a lower electrical conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming a conductive layer over the second oxide semiconductor layer;

etching the conductive layer to form a source electrode and a drain electrode, wherein part of the second oxide semiconductor layer between the source electrode and the drain electrode is etched so that a thickness of the second oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second oxide semiconductor layer below the source electrode and the drain electrode; and

forming an insulating film comprising silicon over the second oxide semiconductor layer, the source electrode and the drain electrode.

14. The method according to claim 5, wherein the insulating film is in contact with an upper surface of the second oxide semiconductor layer between the source electrode and the drain electrode.

20. The method according to claim 5, wherein the first non-single crystalline oxide semiconductor film comprises crystal grains in an amorphous structure.

33. The method according to claim 5, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second oxide semiconductor layer.

6. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate insulating film over a gate electrode;

forming a first non-single crystalline oxide semiconductor film comprising indium, gallium and zinc by sputtering over the gate electrode with the gate insulating film interposed therebetween;

forming a second non-single crystalline oxide semiconductor film comprising indium, gallium and zinc by sputtering over the first non-single crystalline oxide semiconductor film, the second non-single crystalline oxide semiconductor film having a lower electrical conductivity than the first non-single crystalline oxide semiconductor film;

wet etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein at least the first oxide semiconductor layer has a tapered side surface;

forming a conductive layer over the second oxide semiconductor layer;

etching the conductive layer to form a source electrode and a drain electrode, wherein part of the second oxide semiconductor layer between the source electrode and the drain electrode is etched so that a thickness of the second oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second oxide semiconductor layer below the source electrode and the drain electrode; and

forming an insulating film comprising silicon over the second oxide semiconductor layer, the source electrode and the drain electrode.

15. The method according to claim 6, wherein the insulating film is in contact with an upper surface of the second oxide semiconductor layer between the source electrode and the drain electrode.

21. The method according to claim 6, wherein the first non-single crystalline oxide semiconductor film comprises crystal grains in an amorphous structure.

34. The method according to claim 6, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second oxide semiconductor layer.

7. A method of manufacturing a semiconductor device comprising the steps of:

forming a gate insulating film over a gate electrode;

forming a first non-single crystalline oxide semiconductor film comprising indium by sputtering over the gate electrode with the gate insulating film interposed therebetween;

forming a second non-single crystalline oxide semiconductor film comprising indium by sputtering over the first non-single crystalline oxide semiconductor film, the second non-single crystalline oxide semiconductor film having a lower electrical conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming a conductive layer over the second oxide semiconductor layer;

etching the conductive layer to form a source electrode and a drain electrode, wherein part of the second oxide semiconductor layer between the source electrode and the drain electrode is etched so that a thickness of the second oxide semiconductor layer between the source electrode and the drain electrode is smaller than thicknesses of the second oxide semiconductor layer below the source electrode and the drain electrode;

forming a first insulating film comprising silicon and oxygen over the second oxide semiconductor layer, the source electrode and the drain electrode;

forming a second insulating film comprising silicon and nitrogen over the first insulating film; and

heating the first oxide semiconductor layer and the second oxide semiconductor layer at a temperature of 200°

C. to 600°

C.,

wherein an upper surface of the second oxide semiconductor layer between the source electrode and the drain electrode contacts the first insulating film.

11. The method according to claim 7, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

22. The method according to claim 7, wherein the first non-single crystalline oxide semiconductor film comprises crystal grains in an amorphous structure.

35. The method according to claim 7, wherein each of the source electrode and the drain electrode comprises a first titanium layer, a conductive layer on the first titanium layer, and a second titanium layer on the conductive layer, the first titanium layer being in contact with the second oxide semiconductor layer.