Method for forming interlayer connectors to a stack of conductive layers

• US 8,759,217 B1
• Filed: 01/07/2013
• Issued: 06/24/2014
• Est. Priority Date: 01/07/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US13/735,922
• Publication Number:
  US 20140193973A1
• Time in Patent Office: 533 Days
• Field of Search: None
• US Class Current: 438/689
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W−1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M−1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover N^m+1 of the landing areas and the open etch region may cover N^m of the landing areas. N equals 2 plus the number of trimming steps. The trimming step may be carried out so that the increased size open etch region overlies an additional 1/N of the landing areas. Part of the stack surface may be shielded during the removing step to create dummy areas without contact openings.

Claims

1. A method, for use with an electronic device including a stack comprising a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending to respective ones of the plurality of conductive layers, the method comprising:

removing portions of the conductive layers and the dielectric layers in the stack to form landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack, wherein W is the number of conductive layers, the removing step comprising;

etching the stack of dielectric/conductive layers to expose landing areas at W−

1 conductive layers using a set of M etch masks, the etch masks having mask regions and spaced apart open etch regions, with M being greater than or equal to 2, and with N^M being less than or equal to W, where N is an integer greater than or equal to 3;

for each etch mask m in the set, where m goes from 0 to M−

1;

(a) form etch mask m over the contact region, the etch mask having open etch regions over some of the landing areas;

(b) etch through N^m conductive layers at the open etch regions of mask m;

(c) trim etch mask m to increase the size of the open etch regions to overlie additional contact openings;

(d) etch N^m conductive layers at the increased size open etch regions; and

(g) if N is greater than 3, repeat the (c) trim step and the (d) etch step N−

3 times,

whereby the landing areas on the plurality of conductive layers are exposed with different combinations of the etch masks.

2. The method according to claim 1, further comprising:

applying a dielectric fill over the landing areas;

creating contact openings down to the landing areas through the dielectric fill; and

filling the openings with a conductive material thereby forming interlayer connectors.

3. The method according to claim 1, further comprising selecting N as equal to 2 plus the number of trim steps for each etch mask.

4. The method according to claim 1, wherein etch mask 0 has a 0 mask width with an open etch region having an open region width equal to about the 0 mask width divided by N.

5. The method according to claim 1, wherein each etch mask has a mask width with an open etch region having an open region width equal to about the mask width divided by N.

6. The method according to claim 1, wherein in the (a) etch mask forming step, the etch mask covers N^m+1 landing areas and the open etch region covers N^m of the landing areas.

7. The method according to claim 1, wherein in the (a) etch mask forming step, the open etch regions are over about Nm of the landing areas.

8. The method according to claim 1, wherein W=27 and N=3 so that:

for m=1;

the (b) etch step is carried out to etch 1 conductive layer; and

the (d) etch step is carried out to etch 1 conductive layer;

for m=2;

the (b) etch step is carried out to etch 3 conductive layers; and

the (d) etch step is carried out to etch 3 conductive layers; and

for m=3;

the (b) etch step is carried out to etch 9 conductive layers; and

the (d) etch step is carried out to etch 9 conductive layers.

9. The method according to claim 1, wherein the trimming step is carried out so that the increased size open etch regions overlie about an additional 1/N of the landing areas.

10. The method according to claim 1, wherein the device includes a surface over the stack, and further comprising shielding a portion of the surface during the removing step to create dummy areas without contact openings.

11. A method, for use with an integrated circuit device including a stack comprising a plurality of conductive layers interleaved with a plurality of dielectric layers, for forming interlayer connectors extending to respective ones of the plurality of conductive layers, the method comprising:

removing portions of the conductive layers and the dielectric layers in the stack to form landing areas on the plurality of conductive layers in the stack, the landing areas without overlying conductive layers in the stack, wherein said removing includes using a set of M etch masks with M being greater than or equal to 2, and with N^M being less than or equal to W, the etch masks having mask regions and spaced apart open etch regions corresponding to selected landing areas, wherein W is the number of total conductive layers;

for each etch mask m, where m goes from 0 to M−

1, etching N^m conductive layers over up to 1/N of the landing areas, trimming the etch mask m, and etching N^m conductive layers over up to 1/N of the landing areas, so that the landing areas on the plurality of conductive layers are exposed with different combinations of the etch masks.

12. The method according to claim 11, wherein when N=3, each etch mask is trimmed once between etching the conductive layers.

13. The method according to claim 11, wherein when N=4, each etch mask is trimmed twice between etching conductive layers.

14. The method according to claim 11, wherein the spaced apart open etch regions overlie about 1/N of the contact openings.

15. The method according to claim 14, wherein trimming is carried out to create an increased size open etch region overlying about an additional 1/N of the contact openings.

16. The method according to claim 11, further comprising forming interlayer connectors extending to the landing areas of the conductive layers.

17. The method according to claim 16, wherein the interlayer connectors forming step comprises:

filling over the landing areas with a dielectric fill material; and

using a patterned etching process and a conductive material deposition process to form the interlayer connectors extending through the dielectric fill material to the landing areas in the plurality of conductive layers.

18. The method according to claim 11, wherein the device includes a surface over the stack, and further comprising shielding a portion of the surface during the portions removing step.

19. The method according to claim 18, wherein the shielding step is carried out using a hard mask layer at the surface.

20. A set of etch masks for use in exposing landing areas on a plurality of conductive layers interleaved with a plurality of dielectric layers comprising:

a set of M etch masks, the etch masks having mask regions and spaced apart open etch regions, where M is an integer greater than or equal to 2 and N is an integer greater than or equal to 3;

for each etch mask m in the set, where m goes from 0 to M−

1, the etch mask covers landing areas on N^m+1 of the conductive layers and the open etch region covers landing areas on N^m of the conductive layers.