Integration of 3D stacked IC device with peripheral circuits

• US 8,759,899 B1
• Filed: 01/11/2013
• Issued: 06/24/2014
• Est. Priority Date: 01/11/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting, Hsiao, Yi-Hsuan, Chen, Shih-Hung, Shih, Yen-Hao
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/739,914
• Publication Number:
  US 20140197516A1
• Time in Patent Office: 529 Days
• Field of Search: 257/315, 257/506, 257/E21.645
• US Class Current: 257/315
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

Claims

1. An integrated circuit device, comprising:

a substrate including a first region and a second region;

a pit formed in the first region, the pit having a depth;

a stack of active layers alternating with insulating layers deposited in the pit, wherein the stack includes;

a particular insulating layer having a first thickness, wherein a sum of the first thickness of the particular insulating layer, thicknesses of active layers, and thicknesses of other insulating layers in the stack is essentially equal to the depth, the first thickness being different than the thicknesses of the other insulating layers in the stack by an amount within a range of process variations for the depth of the pit, for the thicknesses of active layers, and for the thicknesses of other insulating layers; and

a planarized surface over the first region and the second region, wherein an uppermost one of the active layers has a top surface below the planarized surface;

the integrated circuit device further comprising;

an isolation region in the pit separating the stack from the second region including a peripheral region; and

a stopping layer between the stack and the isolation region and between the isolation region and the peripheral region.

2. The integrated circuit device of claim 1, further comprising components of peripheral circuits over the peripheral region.

3. The integrated circuit device of claim 1, wherein the particular insulating layer includes a bottom insulating layer formed on a bottom of the pit.

4. The integrated circuit device of claim 1, wherein the particular insulating layer is formed on a bottom insulating layer formed on a bottom of the pit, wherein a sum of the first thickness of the particular insulating layer, a second thickness of the bottom insulating layer, thicknesses of active layers, and thicknesses of other insulating layers in the stack is essentially equal to the target depth.

5. The integrated circuit device of claim 1, wherein an uppermost one of the insulating layers is formed on the uppermost one of the active layers, and the particular insulating layer having the first thickness is formed on the uppermost one of the insulating layers.

6. The integrated circuit device of claim 1, wherein the particular insulating layer includes an intermediate insulating layer formed between two adjacent active layers.

7. The integrated circuit device of claim 1, further comprising:

interlayer connectors connected to respective active layers in the stack, the interlayer connectors extending from the respective active layers in the stack in the pit to a connector surface higher than the planarized surface; and

patterned conductor lines on top of the connector surface and connected to the respective interlayer connectors.

8. The integrated circuit device of claim 1, further comprising:

a plurality of active strips including at least a plurality of planes of active strips;

a plurality of structures arranged orthogonally over, and having surfaces conformal with, the plurality of active strips in the plurality of planes; and

memory elements in interface regions at cross-points between side surfaces of active strips in the plurality of planes and the plurality of structures.