Two-dimensional shielded gate transistor device and method of manufacture

• US 8,759,908 B2
• Filed: 11/01/2011
• Issued: 06/24/2014
• Est. Priority Date: 11/01/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik, Bhalla, Anup, Ng, Daniel
• Primary Examiner(s): Maldonado, Julio J.
• Assistant Examiner(s): REIDA, MOLLY KAY
• Application Number:
  US13/286,733
• Publication Number:
  US 20130105886A1
• Time in Patent Office: 966 Days
• Field of Search: None
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The shield electrodes are electrically insulated from the semiconductor substrate and the one or more gate electrodes are electrically insulated from the substrate and shield electrodes.

Claims

1. A shielded gate transistor device, comprising:

a semiconductor substrate;

one or more shield electrodes formed in the semiconductor substrate at a first level, wherein the one or more shield electrodes are electrically insulated from the semiconductor substrate;

one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level, wherein the one or more gate electrodes are electrically insulated from the semiconductor substrate and the one or more shield electrodes, wherein at least a portion of the one or more gate electrodes is oriented non-parallel to the one or more shield electrodes, wherein one or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield trenches.

2. The device of claim 1, wherein the second level is between the one or more shield electrodes and a surface of the semiconductor substrate.

3. The device of claim 1, wherein a pitch of the one or more shield electrodes is different from a pitch of the one or more gate electrodes.

4. The device of claim 1, wherein a width of the one or more shield electrodes is different from a width of the one or more gate electrodes.

5. The device of claim 4, wherein a pitch of the one or more shield electrodes is different from a pitch of the one or more gate electrodes.

6. The device of claim 1, wherein a pitch of the one or more gate electrodes is less than about 2.5 microns.

7. The device of claim 1, wherein a pitch of the one or more gate electrodes is less than about 1 micron.

8. The device of claim 1, wherein at least a portion of the one or more gate electrodes is oriented perpendicular to the one or more shield electrodes.

9. The device of claim 1, wherein at least a portion of the one or more gate electrodes is oriented non-perpendicular to the one or more shield electrodes.

10. The device of claim 1, wherein the one or more gate electrodes include one or more closed cell electrodes.

11. The device of claim 10, wherein the one or more closed cell electrodes include one or more honeycomb closed cell structures.

12. The device of claim 1, wherein the semiconductor substrate includes a drain region of a first conductivity type, the semiconductor substrate further including a body region proximate the one or more gate electrodes, wherein the body region is of a second conductivity type that is opposite the first conductivity type.

13. The device of claim 12, wherein the semiconductor substrate includes a source region proximate the one or more gate electrodes, wherein the source region is of the first conductivity type with a doping concentration higher than that of the drain region, wherein the body region is disposed between the source region and the drain region.

14. The device of claim 13, wherein the first conductivity type is N-type and the second conductivity type is P-type.

15. A method for fabricating a shielded gate transistor device, the method comprising:

a) forming one or more shield electrodes in a semiconductor substrate at a first level, wherein the one or more shield electrodes electrically insulated from the semiconductor substrate;

b) forming one or more gate electrodes in the semiconductor substrate at a second level other than the first level, wherein the one or more gate electrodes are electrically insulated from the semiconductor substrate and the one or more shield electrodes, wherein at least a portion of the one or more gate electrodes is oriented non-parallel to the one or more shield electrodes, wherein one or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield trenches.

16. The method of claim 15, wherein forming the one or more gate electrodes includes forming one or more gate trenches in the semiconductor substrate and forming the one or more gate electrodes in the one or more gate trenches, wherein one or more portions of the one or more gate trenches are oriented non-parallel to the one or more shield electrodes, wherein one or more portions of the one or more gate trenches overlap the one or more shield electrodes.

17. The method of claim 15, wherein the one or more gate electrodes are formed at a level between the one or more shield electrodes and a surface of the semiconductor substrate.

18. The method of claim 15, wherein forming the one or more shield electrodes includes forming one or more shield trenches in a semiconductor substrate;

and

forming the one or more shield electrodes in the one or more shield trenches.

19. The method of claim 18, wherein forming the one or more gate electrodes includes forming one or more gate trenches in the semiconductor substrate at a level between the one or more shield electrodes and a surface of the semiconductor substrate, and forming one or more gate electrodes in the one or more gate trenches, wherein the one or more gate trenches are oriented non-parallel to the one or more shield trenches, wherein one or more portions of the one or more gate trenches overlap the one or more shield trenches.

20. The method of claim 19, wherein a pitch of the one or more shield trenches is different from a pitch of the one or more gate trenches.

21. The method of claim 19, wherein forming the one or more gate trenches includes forming at least a portion of the one or more gate trenches oriented perpendicular to the one or more shield trenches.

22. The method of claim 19, wherein forming the one or more gate trenches includes forming at least a portion of the one or more gate trenches oriented non-perpendicular to the one or more shield trenches.

23. The method of claim 19, wherein forming the one or more gate trenches includes forming one or more closed cell trenches.

24. The method of claim 23, wherein the one or more closed cell trenches include one or more honeycomb closed cell structures.

25. The method of claim 15, wherein the semiconductor substrate includes a drain region of a first conductivity type, the method further comprising forming a body region in the semiconductor substrate proximate the one or more gate electrodes, wherein the body region is of a second conductivity type that is opposite the first conductivity type.

26. The method of claim 25, further comprising forming a source region in the semiconductor substrate proximate the one or more gate electrodes, wherein the source region is of the first conductivity type with a doping concentration higher than that of the drain region, wherein the body region is disposed between the source region and the drain region.

27. The method of claim 15, wherein forming one or more shield trenches includes etching the semiconductor substrate using a first mask having a first trench pattern and wherein forming the one or more gate trenches includes using a second mask having a second trench pattern that is different from the first trench pattern.