Field effect transistor and a method of forming the transistor

• US 8,759,916 B2
• Filed: 01/27/2012
• Issued: 06/24/2014
• Est. Priority Date: 01/27/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bryant, Andres, Nowak, Edward J.
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): BRADLEY, STEPHEN M
• Application Number:
  US13/359,615
• Publication Number:
  US 20130193481A1
• Time in Patent Office: 879 Days
• Field of Search: 257/215, 257/288, 257/347, 257/368, 257/401, 257/328, 257/192, 438/149, 438299-300
• US Class Current: 257/345
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.

Claims

1. A field effect transistor comprising:

an insulator layer;

a semiconductor body having a bottom surface adjacent to said insulator layer and a top surface opposite said bottom surface and comprising;

silicon source/drain regions; and

a silicon alloy channel region positioned laterally between said silicon source/drain regions,

said silicon alloy channel region comprising edge portions adjacent to said silicon source/drain regions and a center portion positioned laterally between and immediately adjacent to said edge portions,

said edge portions and said center portion each comprising a silicon alloy,

said edge portions having a same type conductivity and same conductivity level as said silicon source/drain regions from said top surface to said bottom surface, and

said edge portions and said center portion having any of different types of conductivity and different levels of conductivity;

a gate structure on said top surface of said semiconductor body adjacent to and aligned above said center portion of said silicon alloy channel region; and

gate sidewalls spacers positioned laterally immediately adjacent to said gate structure and further being on said top surface of said semiconductor body adjacent to and aligned above said edge portions of said silicon alloy channel region such that outer surfaces of said gate sidewall spacers are aligned with interfaces between said edge portions of said silicon alloy channel region and said silicon source/drain regions.

2. The field effect transistor of claim 1, said edge portions of said silicon alloy channel region having a different type conductivity than said center portion of said silicon alloy channel region.

3. The field effect transistor of claim 1, said edge portions of said silicon alloy channel region, said silicon source/drain regions and said center portion of said silicon alloy channel region all having said same type conductivity and said edge portions further having a higher level conductivity than said center portion of said silicon alloy channel region.

4. The field effect transistor of claim 1, said field effect transistor comprising a P-type field effect transistor, said silicon alloy channel region comprising any one of silicon germanium and silicon germanium carbide, said silicon source/drain regions and said edge portions of said silicon alloy channel region having a P+ conductivity and said center portion of said channel region having any one of a N-type conductivity and P−

conductivity.

5. The field effect transistor of claim 1, said field effect transistor comprising an N-type field effect transistor, said silicon alloy channel region comprising silicon carbide, said silicon source/drain regions and said edge portions of said silicon alloy channel region having an N+ conductivity and said center portion of said channel region having any one of a P-type conductivity and an N−

conductivity.

6. The field effect transistor of claim 1, said silicon source/drain regions comprising epitaxial silicon layers within recesses adjacent to said edge portions of said silicon alloy channel region.

7. A field effect transistor comprising:

an insulator layer;

a semiconductor fin having a bottom surface adjacent to said insulator layer, a top surface opposite said bottom surface, and opposing sidewalls, said semiconductor fin comprising;

silicon source/drain regions; and

a silicon alloy channel region positioned laterally between said silicon source/drain regions,

said silicon alloy channel region comprising edge portions adjacent to said silicon source/drain regions and a center portion positioned laterally between and immediately adjacent to said edge portions,

said edge portions and said center portion each comprising a silicon alloy,

said edge portions having a same type conductivity and same conductivity level as said silicon source/drain regions from said top surface to said bottom surface, and

said edge portions and said center portion having any of different types of conductivity and different levels of conductivity;

a gate structure on said opposing sidewalls of said semiconductor fin adjacent to and aligned above said center portion of said silicon alloy channel region; and

gate sidewall spacers positioned laterally immediately adjacent to said gate structure and further on said opposing sidewalls of said semiconductor fin adjacent to and aligned with said edge portions of said silicon alloy channel region such that outer surfaces of said gate sidewall spacers are aligned with interfaces between said edge portions of said silicon alloy channel region and said silicon source/drain regions.

8. The field effect transistor of claim 7, said edge portions of said silicon alloy channel region having a different type conductivity than said center portion of said silicon alloy channel region.

9. The field effect transistor of claim 7, said edge portions of said silicon alloy channel region, said silicon source/drain regions and said center portion of said silicon alloy channel region all having said same type conductivity and said edge portions of said silicon alloy channel region further having a higher level conductivity than said center portion of said silicon alloy channel region.

10. The field effect transistor of claim 7, said field effect transistor comprising a P-type field effect transistor, said silicon alloy channel region comprising any one of silicon germanium and silicon germanium carbide, said silicon source/drain regions and said edge portions of said silicon alloy channel region having a P+ conductivity and said center portion of said channel region having any one of a N-type conductivity and P−

conductivity.

11. The field effect transistor of claim 7, said field effect transistor comprising an N-type field effect transistor, said silicon alloy channel region comprising silicon carbide, said silicon source/drain regions and said edge portions of said silicon alloy channel region having an N+ conductivity and said center portion of said channel region having any one of a P-type conductivity and an N−

conductivity.

12. The field effect transistor of claim 7, said silicon source/drain regions comprising epitaxial silicon layers laterally deposited on vertical surfaces of said edge portions of said silicon alloy channel region.

13. A method of forming a field effect transistor comprising:

providing a silicon alloy layer having a bottom surface adjacent to an insulator layer and a top surface opposite said bottom surface;

forming a gate structure on said top surface of said silicon alloy layer adjacent to and aligned above a center portion of a channel region within said silicon alloy layer;

forming gate sidewall spacers positioned laterally immediately adjacent to said gate structure and further positioned on said top surface of said silicon alloy layer and aligned above edge portions of said channel region;

forming recesses in said silicon alloy layer adjacent to said edge portions of said channel region and extending vertically to said insulator layer and filling said recesses with silicon such that outer surfaces of said gate sidewall spacers are aligned with interfaces between said edge portions of said channel region and said silicon, said filling of said recesses comprising performing a lateral epitaxial silicon deposition process; and

simultaneously doping said silicon and said edge portions of said channel region with a dopant to form silicon source/drain regions adjacent to said edge portions of said channel region, to ensure that said edge portions of said channel region have a same type conductivity and same conductivity level as said silicon source/drain regions from said top surface to said bottom surface and to ensure that said edge portions of said channel region and said center portion of said channel region have any of different types of conductivity and different levels of conductivity.

14. The method of claim 13, said silicon alloy layer having a first type conductivity and said dopant having a second type conductivity such that, after said doping, said center portion of said channel region has a different type conductivity than said silicon source/drain regions and said edge portions of said channel region.

15. The method of claim 13, said silicon alloy layer having a first type conductivity and said dopant having said first type conductivity such that, after said doping, said silicon source/drain regions, said edge portion of said channel region and said center portion of said channel region all have said same type conductivity and said center portion of said channel region has a lesser level than said silicon source/drain regions and said edge portions of said channel region.

16. The method of claim 13, said field effect transistor comprising a P-type field effect transistor, said silicon alloy layer comprising a layer of any one of silicon germanium and silicon germanium carbide, said silicon source/drain regions and said edge portions of said channel region having a P+ conductivity and said center portion of said channel region having any one of a N-type conductivity and P−

conductivity.

17. The method of claim 13, said field effect transistor comprising an N-type field effect transistor, said silicon alloy layer comprising a layer of silicon carbide, said silicon source/drain regions and said edge portions of said channel region having an N+ conductivity and said center portion of said channel region having any one of a P-type conductivity and an N−

conductivity.

18. A method of forming a field effect transistor comprising:

forming a silicon alloy fin having a bottom surface adjacent to an insulator layer, a top surface opposite said bottom surface and opposing sidewalls;

forming a gate structure on said opposing sidewalls and said top surface of said silicon alloy fin aligned with a center portion of a channel region within said silicon alloy fin;

forming gate sidewall spacers positioned laterally immediately adjacent to said gate structure and on said opposing sidewalls and said top surface of said silicon alloy fin adjacent to and aligned with edge portions of said channel region within said silicon alloy fin such that outer sections of said silicon alloy fin remain exposed;

removing said outer sections such that said insulator layer and side surfaces of said edge portions of said channel region are exposed and depositing silicon on said side surfaces such that outer surfaces of said gate sidewall spacers are aligned with interfaces between said side surfaces of said edge portions of said channel region and said silicon, said depositing comprising performing a lateral epitaxial silicon deposition process; and

simultaneously doping said silicon and said edge portions of said channel region with a dopant to form silicon source/drain regions adjacent to said edge portions of said channel region, to ensure that said edge portions of said channel region have a same type conductivity and same conductivity level as said silicon source/drain regions from said top surface to said bottom surface, and to ensure that said edge portions of said channel region and said center portion of said channel region have any of different types of conductivity and different levels of conductivity.

19. The method of claim 18, said silicon alloy fin having a first type conductivity and said dopant having a second type conductivity such that, after said doping, said center portion of said channel region has a different type conductivity than said silicon source/drain regions and said edge portions of said channel region.

20. The method of claim 18, said silicon alloy fin having a first type conductivity and said dopant having said first type conductivity such that, after said doping, said center portion of said channel region has a same type conductivity at a lesser level than said silicon source/drain regions and said edge portions of said channel region.

21. The method of claim 18, said field effect transistor comprising a P-type field effect transistor, said silicon alloy fin comprising any one of silicon germanium and silicon germanium carbide, said silicon source/drain regions and said edge portions of said silicon alloy channel region having a P+ conductivity and said center portion of said channel region having any one of a N-type conductivity and P−

conductivity.

22. The method of claim 18, said field effect transistor comprising an N-type field effect transistor, said silicon alloy fin comprising silicon carbide, said silicon source/drain regions and said edge portions of said silicon alloy channel region having an N+ conductivity and said center portion of said channel region having any one of a P-type conductivity and an N−

conductivity.

23. The method of claim 18, said forming of said silicon alloy fin further comprising forming multiple silicon alloy fins,

said gate structure and said gate sidewall spacers being formed so as to traverse all channel regions of all of said silicon alloy fins,

said removing being performed so as to remove all outer sections of all of said silicon alloy fins, and

said depositing being performed such that said silicon is deposited on all side surfaces of all edge portions of all of said channel regions.