Thin-film transistor having etch stop multi-layer and method of manufacturing the same

• US 8,759,917 B2
• Filed: 12/28/2010
• Issued: 06/24/2014
• Est. Priority Date: 01/04/2010
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Joon Seok, Kim, Tae Sang, Choi, Yun-Hyuk
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US12/929,066
• Publication Number:
  US 20110163310A1
• Time in Patent Office: 1,274 Days
• Field of Search: 257/347
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin-film transistor (TFT) may include a channel layer, an etch stop multi-layer, a source, a drain, a gate, and a gate insulation layer. The etch stop multi-layer may include a first etch stop layer and a second etch stop layer. The second etch stop layer may prevent or reduce an etchant from contacting the channel layer.

Claims

1. A thin-film transistor (TFT) comprising:

a gate insulation layer on a gate;

a channel layer on the gate insulation layer, the gate corresponding with the channel layer;

first and second etch stop layers sequentially stacked on a portion of the channel layer, the first and second etch stop layers being formed of a same material, and the second etch stop layer being structurally denser than the first etch stop layer;

a source and a drain contacting ends of the channel layer; and

a passivation layer on the at least two etch stop layers, the source and the drain.

2. The TFT of claim 1, wherein the channel layer includes an oxide semiconductor.

3. The TFT of claim 2, wherein the oxide semiconductor comprises at least one material selected from the group consisting of zinc oxide, gallium indium zinc oxide, and hafnium indium zinc oxide.

4. The TFT of claim 1, wherein the second etch stop layer is formed at a temperature higher than a temperature at which the first etch stop layer is formed.

5. The TFT of claim 1, wherein the at least two etch stop layers further comprise at least one third etch stop layer on at least one of the first etch stop layer and the second etch stop layer.

6. The TFT of claim 5, wherein the third etch stop layer is structurally denser than the first etch stop layer.

7. The TFT of claim 1, wherein the first and second etch stop layers include at least one material selected from the group consisting of silicon oxide (SiO_x), silicon nitride (SiN_x), aluminum oxide (Al_xO_x), silicon oxynitride (SiON), fluorinated silicon oxide (SiOF), and silicon oxycarbide (SiOC).

15. The TFT of claim 1, wherein each of the first and second etch stop layers has a thickness between about 20 nm and about 200 nm.

16. The TFT of claim 1, wherein the passivation layer is conformally formed along at least a top surface of the first and second etch stop layers, the source and the drain.

17. The TFT of claim 1, wherein the source and the drain contact a top surface and a side surface of the channel layer.

18. The TFT of claim 1, wherein the source and the drain contact the first and second etch stop layers.

8. A method of manufacturing a thin film transistor (TFT), the method comprising:

forming a gate insulation layer on a gate;

forming a channel layer on the gate insulation layer, the channel layer corresponding to the gate;

forming first and second etch stop layers sequentially stacked on the channel layer, the first and second etch stop layers covering a portion of the channel layer and being formed of a same material, the second etch stop layer being structurally denser than the first etch stop layer;

forming a source and a drain on each end of the channel layer; and

forming a passivation layer on the at least two etch stop layers, the source, and the drain.

9. The method of claim 8, wherein the channel layer is formed of an oxide semiconductor.

10. The method of claim 9, wherein the oxide semiconductor comprises at least one material selected from the group consisting of zinc oxide, gallium indium zinc oxide, and hafnium indium zinc oxide.

11. The method of claim 8, wherein the first etch stop layer is formed at a temperature lower than a temperature at which the second etch stop layer is formed.

12. The method of claim 8, wherein the first etch stop layer is formed at a first temperature range between about 100°

C. and about 250°

C. and the second etch stop layer is formed at a second temperature range between about 250°

C. and about 400°

C.

13. The method of claim 8, further comprising:

forming at least one etch stop layer on the second etch stop layer.

14. The method of claim 8, wherein the first and second etch stop layers are formed of at least one material selected from the group consisting of silicon oxide (SiO_x), silicon nitride (SiN_x), aluminum oxide (Al_xO_x), silicon oxynitride (SiON), fluorinated silicon oxide (SiOF), and silicon oxycarbide (SiOC).