Schottky junction diode devices in CMOS with multiple wells

• US 8,759,937 B2
• Filed: 03/22/2006
• Issued: 06/24/2014
• Est. Priority Date: 03/30/2005
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Ma, Yanjun, Oliver, Ronald A., Humes, Todd E., Mavoori, Jaideep
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US11/387,515
• Publication Number:
  US 20060223246A1
• Time in Patent Office: 3,016 Days
• Field of Search: 257/371, 257/E21.359, 257/E21.368, 257/E29.338, 257471-486, 257544-551
• US Class Current: 257/484
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.

Claims

1. A Schottky junction diode device, comprising:

a substrate including substrate material of a first conductivity type and first dopant concentration;

a first well, disposed in the substrate, including material of a second conductivity type and second dopant concentration, the second conductivity type opposite to the first conductivity type;

a second well, disposed in the first well, including material of the first conductivity type and third dopant concentration;

a second well contact within the second well, the second well contact comprising contact material of the first conductivity type and fourth dopant concentration higher than the first or the third dopant concentration;

a region of metal-containing material disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well;

a third well, disposed in the substrate, including material of the first conductivity type and fifth dopant concentration lower than the fourth dopant concentration, wherein a portion of the substrate material of the first conductivity type and the first dopant concentration separates the third well and the first well to reduce capacitance of the Schottky junction diode device; and

a third well contact within the third well, the third well contact comprising contact material of the first conductivity type and sixth dopant concentration higher than the fifth dopant concentration.

2. The device of claim 1, further comprising a first well contact included within the first well, the first well contact of the second conductivity type and a seventh dopant concentration higher than the second dopant concentration.

3. The device of claim 1, wherein the second well contact is formed in a closed loop shape which surrounds the Schottky junction.

4. The device of claim 3, wherein the closed loop shape is a rectangle.

5. The device of claim 2, wherein the first well contact is formed in a closed loop shape which surrounds the Schottky junction.

6. The device of claim 5, wherein the closed loop shape is a rectangle.

7. The device of claim 1, wherein the third well contact is formed in a closed loop shape which surrounds the Schottky junction.

8. The device of claim 7, wherein the closed loop shape is a rectangle.

9. The device of claim 1, wherein the substrate includes silicon.

10. The device of claim 1, wherein the substrate includes gallium arsenide.

11. The device of claim 1, wherein the region of metal-containing material comprises one or more of the materials selected from the group consisting of:

titanium, titanium silicide, cobalt, cobalt silicide, nickel, nickel silicide, tungsten, tungsten silicide, gold, manganese, hafnium, silver, aluminum, palladium and platinum.

12. The device of claim 1, where the first dopant concentration is in an order of 10¹⁵ atoms of dopants per cubic centimeter.

13. The device of claim 1, wherein the second dopant concentration is in an order of 10¹⁷ atoms of dopants per cubic centimeter.

14. The device of claim 1, wherein the third dopant concentration is in an order of 10¹⁷ atoms of dopants per cubic centimeter.

15. The device of claim 1, wherein the fourth dopant concentration in an order of 10²⁰ atoms of dopants per cubic centimeter.

16. The device of claim 1, wherein the fifth dopant concentration is in an order of 10¹⁷ atoms of dopants per cubic centimeter.

17. The device of claim 1, wherein the sixth dopant concentration is in an order of 10²⁰ atoms of dopants per cubic centimeter.

18. The device of claim 1, wherein the device is manufactured using a standard Complementary Metal-Oxide-Semiconductor (CMOS) process.

19. The device of claim 1, wherein a bias signal to the substrate is applied via the third well.

20. A method for manufacturing a Schottky junction diode device, comprising:

forming a substrate including substrate material of a first conductivity type and first dopant concentration;

forming a first well, disposed in the substrate, including material of a second conductivity type and second dopant concentration, the second conductivity type opposite to the first conductivity type;

forming a second well, disposed in the first well, including material of the first conductivity type and third dopant concentration;

forming a second well contact within the second well, the second well contact comprising contact material of the first conductivity type and fourth dopant concentration higher than the first or the third dopant concentration;

forming a region of metal-containing material disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well;

forming a third well disposed in the substrate and separated from the first well by a part of the substrate material of the first conductivity type and the first dopant concentration to reduce capacitance of the Schottky junction diode device, the third well including material of the first conductivity type and fifth dopant concentration lower than the fourth dopant concentration; and

forming a third well contact within the third well, the third well contact comprising contact material of the first conductivity type and sixth dopant concentration higher than the fifth dopant concentration.

21. The method of claim 20, further comprising:

forming a first well contact within the first well, the first well contact of the second conductivity and a seventh dopant concentration higher than the second dopant concentration.

22. The method of claim 20, wherein said forming a region of metal-containing material comprises utilizes one or more of the materials selected from the group consisting of:

titanium, titanium silicide, cobalt, cobalt silicide, nickel, nickel silicide, tungsten, tungsten silicide, gold, manganese, hafnium, silver, aluminum, palladium and platinum to form the metal-containing region.

23. The method of claim 20, wherein said forming a second well contact includes forming the second well contact in a closed loop shape on a surface of the second well surrounding the region of metal-containing material.

24. The method of claim 23, wherein the closed loop shape is a rectangle.

25. The method of claim 20, wherein said forming a third well contact includes forming the third well contact in a closed loop shape on a surface of the third well surrounding the region of metal-containing material.

26. The method of claim 25, wherein the closed loop shape is a rectangle.

27. The method of claim 20, wherein the second dopant concentration is in an order of 10¹⁷ atoms of dopants per cubic centimeter.

28. The method of claim 20, wherein the third dopant concentration is in an order of 10¹⁷ atoms of dopants per cubic centimeter.

29. The method of claim 20, wherein the fourth dopant concentration in an order of 10²⁰ atoms of dopants per cubic centimeter.

30. The method of claim 20, wherein the fifth dopant concentration is in an order of 10¹⁷ atoms of dopants per cubic centimeter.

31. The method of claim 20, wherein the sixth dopant concentration is in an order of 10²⁰ atoms of dopants per cubic centimeter.

33. The method of claim 20, wherein a bias signal to the substrate is applied via the third well.

32. The method of clam 20, wherein the first well, forming the second well, forming the second well contact, forming the region of metal-containing material, forming the third well, and forming the third well contact are part of a standard Complementary Metal-Oxide-Semiconductor (CMOS) process.