Microelectronic assemblies having compliancy and methods therefor

• US 8,759,973 B2
• Filed: 12/22/2011
• Issued: 06/24/2014
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Oganesian, Vage, Gao, Guilian, Haba, Belgacem, Ovrutsky, David
• Primary Examiner(s): WHALEN, DANIEL B
• Application Number:
  US13/335,022
• Publication Number:
  US 20120091582A1
• Time in Patent Office: 915 Days
• Field of Search: None
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Claims

1. A microelectronic assembly comprising:

a semiconductor wafer having a first surface and contacts accessible at the first surface;

a plurality of compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, the plurality of compliant bumps having coplanar top surfaces;

conductive traces electrically connected with the contacts and extending therefrom to overlie the coplanar top surfaces of the compliant bumps;

a first dielectric layer having openings and overlying the conductive traces;

a second dielectric layer overlying the first surface of the semiconductor wafer and at least edges of the compliant bumps; and

conductive elements overlying the coplanar top surfaces, the conductive elements extending through the openings in the first dielectric layer and in contact with the conductive traces.

2. The assembly as claimed in claim 1, wherein the conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

3. The assembly as claimed in claim 1, further comprising a circuit panel, wherein the conductive elements include terminals of the assembly for electrical connection with corresponding contact elements of the circuit panel.

4. The assembly as claimed in claim 3, wherein the terminals include at least one terminal which is disposed singly atop one of the plurality of compliant bumps.

5. The assembly as claimed in claim 3, wherein the terminals are bonded to the contact elements of the circuit panel.

6. The assembly as claimed in claim 1, wherein the semiconductor wafer comprises one or more memory chips.

7. The assembly as claimed in claim 1, wherein the conductive elements are rigid solid metal posts.

8. The assembly as claimed in claim 7, wherein the rigid solid metal posts are frustoconical.

9. The assembly as claimed in claim 7, wherein the rigid solid metal posts are plated posts.

10. The assembly as claimed in claim 7, wherein the rigid solid metal posts have a height above the top surface of the compliant layer ranging from 50-300 micrometers.

11. A microelectronic assembly comprising:

a semiconductor wafer having a first surface and contacts accessible at the first surface;

compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, each of the compliant bumps having a planar top surface;

a first dielectric layer overlying the first surface of the semiconductor wafer and at least edges of the compliant bumps, wherein the planar top surfaces of the compliant bumps and the contacts are accessible through the dielectric layer;

conductive traces electrically connected with the contacts and extending therefrom to overlie the planar top surfaces of the compliant bumps;

a second dielectric layer having openings, portions of the conductive traces being exposed through the openings; and

conductive elements overlying the planar top surfaces in contact with the conductive traces.

12. The assembly as claimed in claim 11, wherein the first dielectric layer includes a photoimageable material.

13. The assembly as claimed in claim 12, wherein the photoimageable material includes silicone.

14. The assembly as claimed in claim 11, wherein the first dielectric layer is compliant.

15. The assembly as claimed in claim 11, wherein the conductive elements are selected from the group consisting of solder balls, conductive posts and conductive pins.

16. The assembly as claimed in claim 11, further comprising a circuit panel, wherein the conductive elements include terminals of the assembly for electrical connection with corresponding contact elements of a circuit panel.

17. The assembly as claimed in claim 16, wherein the terminals include at least one terminal which is disposed singly atop one of the compliant bumps.

18. The assembly, as claimed in claim 11, wherein the conductive elements are rigid solid metal posts.

19. The assembly as claimed in claim 18, wherein the conductive posts are frustoconical.

20. The assembly as claimed in claim 18, wherein the conductive posts have a height above the top surface of the compliant layer ranging from 50-300 micrometers.