Runtime loading of configuration data in a configurable IC

• US 8,760,194 B2
• Filed: 10/25/2011
• Issued: 06/24/2014
• Est. Priority Date: 07/15/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Khubehandani, Teju, Schmit, Herman, Teig, Steven, Hutchings, Brad
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/281,425
• Publication Number:
  US 20120098567A1
• Time in Patent Office: 973 Days
• Field of Search: 326 38- 41
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.

Claims

1. An integrated circuit (IC) comprising:

an arrangement of configurable tiles, each configurable tile comprising configurable circuits for configurably performing operations based on configuration data; and

a pipelined network comprising a plurality of M-bit wide segments, each M-bit wide segment defined by a plurality of M-bit wide storage elements, each storage element for providing M-bits of data to one configurable tile in the arrangement in each clock cycle, M being an integer greater than one, wherein the pipelined network allows a plurality of sets of data to traverse the arrangement of configurable tiles simultaneously at different segments of the pipelined network.

2. The IC of claim 1, wherein each segment comprises storage elements associated with configurable tiles that are vertically or horizontally aligned.

3. The IC of claim 1, wherein at least one set of the plurality of sets of data simultaneously traversing the pipelined network is monitored data from a configurable tile.

4. The IC of claim 1, wherein the plurality of sets of data are for configuring configurable circuits in individual configurable tiles in the arrangement.

5. The IC of claim 1, wherein at least two of the plurality of sets of data simultaneously traversing the pipelined network are for configuring configurable logic circuits in different configurable tiles in the arrangement.

6. The IC of claim 1, wherein at least two of the plurality of sets of data simultaneously traversing the pipelined network are for configuring configurable logic circuits in a same configurable tile.

7. The IC of claim 1, wherein two consecutive storage elements in a segment of the pipelined network carry data from different sets of the plurality of sets of data.

8. An electronic device comprising:

an integrated circuit (IC), the IC comprising;

an arrangement of configurable tiles, each configurable tile comprising configurable circuits for configurably performing operations based on configuration data; and

a pipelined network comprising a plurality of M-bit wide segments, each M-bit wide segment defined by a plurality of M-bit wide storage elements, each storage element for providing M-bits of data to one configurable tile in the arrangement in each clock cycle, M being an integer greater than one, wherein the pipelined network allows a plurality of sets of data to traverse the arrangement of configurable tiles simultaneously at different segments of the pipelined network; and

a memory device for providing the configuration data to the IC.

9. The electronic device of claim 8, wherein each segment comprises storage elements associated with configurable tiles that are vertically or horizontally aligned.

10. The electronic device of claim 8, wherein at least one set of the plurality of sets of data simultaneously traversing the pipelined network is monitored data from a configurable tile.

11. The electronic device of claim 8, wherein the plurality of sets of data traverse the pipelined network are for configuring configurable circuits in individual configurable tiles in the arrangement.

12. The electronic device of claim 8, wherein at least two of the plurality of sets of data simultaneously traversing the pipelined network are for configuring configurable logic circuits in different configurable tiles in the arrangement.

13. The electronic device of claim 8, wherein at least two of the plurality of sets of data simultaneously traversing the pipelined network are for configuring configurable logic circuits in a same configurable tile.

14. The electronic device of claim 8, wherein two consecutive storage elements in a segment of the pipelined network carry data from different sets of the plurality of sets of data.

15. An integrated circuit (IC) comprising:

an arrangement of configurable tiles, each configurable tile comprising configurable circuits for configurably performing operations based on configuration data; and

a pipelined network comprising a plurality of pipelined segments each segment comprising a plurality of M-bit wide pipeline stages, each pipeline stage comprising a M-bit wide register associated with a set of configurable tiles in the arrangement, M being an integer greater than one, wherein the pipelined network allows a plurality of sets of data to traverse the arrangement of configurable tiles simultaneously at different segments of the pipelined network.

16. The IC of claim 15, wherein the set of configurable tiles associated with a segment are vertically or horizontally aligned.

17. The IC of claim 15, wherein at least one set of the plurality of sets of data simultaneously traversing the pipelined network is monitored data from a configurable tile.

18. The IC of claim 15, wherein the plurality of sets of data traversing the pipelined network are for configuring configurable circuits in individual configurable tiles in the arrangement.

19. The IC of claim 15, wherein at least two of the plurality of sets of data simultaneously traversing the pipelined network are for configuring configurable logic circuits in different configurable tiles in the arrangement.

20. The IC of claim 15, wherein at least two of the plurality of sets of data simultaneously traversing the pipelined network are for configuring configurable logic circuits in a same configurable tile.