System for generating clock signal

• US 8,760,202 B1
• Filed: 05/15/2013
• Issued: 06/24/2014
• Est. Priority Date: 05/15/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sinha, Samaksh, Gupta, Sunny, Gupta, Niti
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/895,344
• Time in Patent Office: 405 Days
• Field of Search: 327147-149, 327156-158
• US Class Current: 327/157
• CPC Class Codes: H03L 2207/08 Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence

Abstract

A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.

Claims

1. A system for generating a clock signal, comprising:

a phase-locked loop (PLL), including;

a phase-frequency detector (PFD), that generates an error signal based on an input reference signal and a feedback signal;

a charge pump, connected to the PFD, that generates a charge pump current based on the error signal;

a low pass filter (LPF) having an input terminal connected to the charge pump for generating a control voltage based on the charge pump current;

a voltage-controlled oscillator (VCO), connected to an output terminal of the LPF, that generates the clock signal having a frequency proportional to the control voltage; and

a frequency divider, connected between the VCO and the PFD, that generates the feedback signal by adjusting a frequency of the clock signal; and

a voltage storage circuit, including;

a unity-gain amplifier (UGA) having an input terminal and an output terminal;

a first switch, connected between the input terminal of the UGA and the output terminal of the LPF, for disconnecting the input terminal of the UGA from the output terminal of the LPF when the PLL is in a STOP mode, and connecting the input terminal of the UGA and the output terminal of the LPF, for sampling the control voltage for a first predefined period when the PLL is in a RUN mode;

a second switch, connected between the output and input terminals of the UGA, for disconnecting the output and input terminals of the UGA when the PLL is in the RUN mode, and connecting the output and input terminals of the UGA at the end of the first predefined period, for storing the sampled control voltage when the PLL is in the STOP mode; and

a third switch, connected between the output terminal of the UGA and an input terminal of the LPF, for disconnecting the output terminal of the UGA from the input terminal of the LPF when the PLL is in the STOP mode, and connecting the output terminal of the UGA and the input terminal of the LPF for providing the stored control voltage to the input terminal of the LPF, for a second predefined period when the PLL transitions from the STOP mode to the RUN mode.

2. The system of claim 1, further comprising a control unit for controlling switching of the first, second and third switches.

3. The system of claim 2, wherein the control unit disables the voltage storage circuit and enables the PLL when the PLL enters the RUN mode.

4. The system of claim 2, wherein the control unit disables the PLL when the PLL enters the STOP mode.

5. The system of claim 1, wherein the voltage storage circuit further comprises a voltage multiplier, connected between the output terminal of the UGA and the third switch, for adjusting the stored control voltage based on a predetermined frequency of the clock signal.

6. The system of claim 1, wherein the first, second and third switches each include a complementary metal-oxide semiconductor (CMOS) transmission gate.

7. A system for generating a clock signal, comprising:

a phase-locked loop (PLL), including;

a phase-frequency detector (PFD), that generates an error signal based on an input reference signal and a feedback signal;

a charge pump, connected to the PFD, that generates a charge pump current based on the error signal;

a low pass filter (LPF) having an input terminal connected to the charge pump for generating a control voltage based on the charge pump current;

a voltage-controlled oscillator (VCO), connected to an output terminal of the LPF, that generates the clock signal having a frequency proportional to the control voltage; and

a frequency divider, connected between the VCO and the PFD, that generates the feedback signal by adjusting a frequency of the clock signal; and

a voltage storage circuit, including;

a unity-gain amplifier (UGA) having an input terminal and an output terminal;

a first switch, connected between the input terminal of the UGA and the output terminal of the LPF, for disconnecting the input terminal of the UGA from the output terminal of the LPF when the PLL is in a STOP mode, and connecting the input terminal of the UGA and the output terminal of the LPF, for sampling the control voltage for a first predefined period when the PLL is in a RUN mode;

a second switch, connected between the output and input terminals of the UGA, for disconnecting the output and input terminals of the UGA when the PLL is in the RUN mode, and connecting the output and input terminals of the UGA at the end of the first predefined period, for storing the sampled control voltage when the PLL is in the STOP mode;

a voltage multiplier, connected to the output terminal of the UGA, for adjusting the stored control voltage based on a predetermined frequency of the clock signal; and

a third switch, connected between an output terminal of the voltage multiplier and an input terminal of the LPF, for disconnecting the output terminal of the voltage multiplier from the input terminal of the LPF when the PLL is in the STOP mode, and connecting the output terminal of the voltage multiplier and the input terminal of the LPF for providing the stored control voltage to the input terminal of the LPF, for a second predefined period when the PLL transitions from the STOP mode to the RUN mode.

8. The system of claim 7, further comprising a control unit for controlling switching of the first, second and third switches.

9. The system of claim 8, wherein the control unit disables the voltage storage circuit and enables the PLL when the PLL transitions from the STOP mode to the RUN mode.

10. The system of claim 8, wherein the control unit disables the PLL when the PLL transitions from the STOP mode to the RUN mode.

11. The system of claim 7, wherein the first, second and third switches each include a complementary metal-oxide semiconductor (CMOS) transmission gate.