Apparatus and methods for quadrature clock signal generation
First Claim
1. An apparatus comprising:
- a sine-shaping filter configured to receive a clock input signal and to filter the clock input signal to generate a sinusoidal clock signal; and
a polyphase filter configured to receive the sinusoidal clock signal and to generate an in-phase clock signal and a quadrature-phase clock signal based on the sinusoidal clock signal,wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature phase relationship,wherein the polyphase filter comprises a first stage including a first plurality of resistors and a first plurality of capacitors, wherein the first stage is associated with a first pole of a transfer function of the polyphase filter.
1 Assignment
0 Petitions
Accused Products
Abstract
Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.
-
Citations
21 Claims
-
1. An apparatus comprising:
-
a sine-shaping filter configured to receive a clock input signal and to filter the clock input signal to generate a sinusoidal clock signal; and a polyphase filter configured to receive the sinusoidal clock signal and to generate an in-phase clock signal and a quadrature-phase clock signal based on the sinusoidal clock signal, wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature phase relationship, wherein the polyphase filter comprises a first stage including a first plurality of resistors and a first plurality of capacitors, wherein the first stage is associated with a first pole of a transfer function of the polyphase filter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. An apparatus, comprising:
-
a sine-shaping filter configured to receive a clock input signal and to filter the clock input signal to generate a sinusoidal clock signal; a polyphase filter configured to receive the sinusoidal clock signal and to generate an in-phase clock signal and a quadrature-phase clock signal based on the sinusoidal clock signal, wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature phase relationship; a buffer circuit configured to buffer the in-phase clock signal to generate an in-phase sinusoidal reference clock signal and to buffer the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship; a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal; and a sampler configured to receive a serial data stream and to sample the serial data stream on at least one of a rising edge of a sampling clock signal and a falling edge of the sampling clock signal, wherein the phase interpolator is configured to generate the sampling clock signal based on the interpolated clock signal.
-
-
13. An apparatus comprising:
-
a sine-shaping filter configured to receive a clock input signal and to filter the clock input signal to generate a sinusoidal clock signal; a polyphase filter configured to receive the sinusoidal clock signal and to generate an in-phase clock signal and a quadrature-phase clock signal based on the sinusoidal clock signal, wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature phase relationship; a buffer circuit configured to buffer the in-phase clock signal to generate an in-phase sinusoidal reference clock signal and to buffer the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship; and a regulator configured to generate a regulated voltage, wherein the regulator is configured to power at least a portion of the buffer circuit using the regulated voltage.
-
-
14. An apparatus comprising:
-
a sine-shaping filter configured to receive a clock input signal and to filter the clock input signal to generate a sinusoidal clock signal; a polyphase filter configured to receive the sinusoidal clock signal and to generate an in-phase clock signal and a quadrature-phase clock signal based on the sinusoidal clock signal, wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature phase relationship; and a buffer circuit configured to buffer the in-phase clock signal to generate an in-phase sinusoidal reference clock signal and to buffer the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship, wherein the clock input signal, the sinusoidal clock signal, the in-phase clock signal, the quadrature-phase clock signal, the in-phase sinusoidal reference clock signal, and the quadrature-phase sinusoidal reference clock signal are differential signals. - View Dependent Claims (15)
-
-
16. An apparatus comprising:
-
a sine-shaping filter configured to receive a clock input signal and to filter the clock input signal to generate a sinusoidal clock signal; a polyphase filter configured to receive the sinusoidal clock signal and to generate an in-phase clock signal and a quadrature-phase clock signal based on the sinusoidal clock signal, wherein the in-phase clock signal and the quadrature-phase clock signal have a quadrature phase relationship; and a buffer circuit configured to buffer the in-phase clock signal to generate an in-phase sinusoidal reference clock signal and to buffer the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship, wherein the buffer circuit comprises a first buffer inverter, a second buffer inverter, a first buffer resistor, and a second buffer resistor, and wherein the first buffer inverter includes an input configured to receive the in-phase clock signal and an output configured to generate the in-phase sinusoidal reference clock signal, and wherein the second buffer inverter includes an input configured to receive the quadrature-phase clock signal and an output configured to generate the quadrature-phase sinusoidal reference clock signal, and wherein the first buffer resistor is electrically connected between the input and the output of the first buffer inverter, and wherein the second buffer resistor is electrically connected between the input and the output of the second buffer inverter.
-
-
17. A method of clock signal generation, the method comprising:
-
filtering a clock input signal to generate a sinusoidal clock signal using a sine-shaping filter; generating an in-phase clock signal and a quadrature-phase clock signal from the sinusoidal clock signal using a polyphase filter, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship; buffering the in-phase clock signal to generate an in-phase sinusoidal reference clock signal using a buffer circuit; buffering the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal using the buffer circuit, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship; generating an interpolated clock signal using a phase interpolator, wherein the interpolated clock signal is based on a weighted sum of the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal; and generating a sampling clock signal based on the interpolated clock signal and sampling a serial data stream using the sampling clock signal. - View Dependent Claims (18)
-
-
19. A method of clock signal generation comprising:
-
filtering a clock input signal to generate a sinusoidal clock signal using a sine-shaping filter; generating an in-phase clock signal and a quadrature-phase clock signal from the sinusoidal clock signal using a polyphase filter, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship; buffering the in-phase clock signal to generate an in-phase sinusoidal reference clock signal using a buffer circuit; and buffering the quadrature-phase clock signal to generate a quadrature-phase sinusoidal reference clock signal using the buffer circuit, wherein the in-phase sinusoidal reference clock signal and the quadrature-phase sinusoidal reference clock signal have a quadrature phase relationship, generating a regulated voltage for the buffer circuit using a regulator. - View Dependent Claims (20, 21)
-
Specification