Article conveying system and sample processing system

• US 8,760,264 B2
• Filed: 07/20/2010
• Issued: 06/24/2014
• Est. Priority Date: 07/29/2009
• Status: Active Grant

• Current Assignee: Hitachi High-Tech Company Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Onizawa, Kuniaki, Kiyonari, Yoshio, Oba, Shigemi, Fukugaki, Tatsuya
• Primary Examiner(s): Mehmood, Jennifer
• Assistant Examiner(s): Jiang, Yong Hang
• Application Number:
  US13/386,718
• Publication Number:
  US 20120133492A1
• Time in Patent Office: 1,435 Days
• Field of Search: 340/10.1, 340/10.4, 340/10.5, 340/10.51, 340/10.52, 340/5.1, 705/28, 235/385, 209/511, 209/517, 209/518, 209/521, 209/524, 209/527, 209/536, 209/539, 209/552, 209/559, 209/576, 209/577, 209/578, 209/579, 209/581, 209/582
• US Class Current: 340/10.51
• CPC Class Codes: G01N 2035/0094 optimisation; experiment design
• CPC Class Codes: G01N 2035/0472 for selective recirculation of carriers
• CPC Class Codes: G01N 35/00732 Identification of carriers, materials or components in automatic analysers
• CPC Class Codes: G01N 35/0092 Scheduling
• CPC Class Codes: G01N 35/026 having blocks or racks of reaction cells or cuvettes

Abstract

An object of the present invention is to provide a sample processing system, wherein writing to each RFID is equalized to eliminate unevenness in the use of sample containers.

The configuration of the present invention can be realized by controlling the numbers of times (write counts) data is written to RFIDs, and by skipping data writing according to frequencies in the use of sample containers.

Setting use information (count) of each IC tag, and comparing the use information with an average value of the use of the IC tags, make it possible to limit the write counts, which enables the equalization of writing to the IC tags, thereby making it possible to uniform the use of the sample containers in the system.

Claims

1. A sample conveying system comprising:

a conveying line for conveying sample container holders, each of which sample container holders can hold and remove a sample container, to a sample processing unit;

an erase/unload unit for supplying the sample container to the conveying line and for removing the sample container from the conveying line;

a write means for storing a write count of writing information to each of non-volatile semiconductor memories each of which non-volatile semiconductor memories is attached to one of the sample container holders conveyed from the erase/unload unit;

a write count comparison mechanism for comparing the write count of writing information stored by the write means with a threshold value;

a return line for returning the sample container holders, which are finished with processes of the sample processing unit, to an upper stream of the write means;

a conveying line control mechanism for controlling the conveying line and the return line to return each sample container holder including its non-volatile semiconductor memory to skip the writing operation into the semiconductor memories by using the write means and to return the sample container holder into the upper stream of the write means, when the write count comparison mechanism has judged that the write count of the semiconductor memory is larger than the threshold value; and

a reconveying line included in the conveying line, the re-conveying line conveying the sample container holder being returned into the upper stream of the write means by the conveying line control mechanism to the write means from the stream of the write means.

2. The sample conveying system according to claim 1, wherein the write count comparison mechanism compares the write count with a plurality of threshold values, and the control for conveying the sample container holder by the conveying line is changed on the basis of the judgment of the write count comparison mechanism which judges whether or not the write count is larger than a plurality of threshold values.

3. The sample conveying system according to claim 2, further comprising a bypass line to return the sample container holder into the upper stream of the write means through a bypass line route which is shorter than the return line,

wherein the write count comparison mechanism compares the write count stored in the semiconductor memory with the threshold value, and controls a conveying line in response to whether the return line or the bypass line is used for conveying the sample container holder on the basis of the judgment whether the write count stored in the memory is larger than the plurality of threshold values.

4. The sample conveying system according to claim 1, wherein the write count comparison mechanism compares the write count of writing information by the write means with a plurality of threshold values including a first threshold value and a second threshold value;

wherein the conveying line control mechanism controls the conveying line to convey the sample container holders through a bypass line into the upper stream of the write means when the write count is larger than the first threshold value and smaller than the second threshold value; and

wherein the conveying line control mechanism controls the conveying line to convey the sample container holders through the return line to the upper stream of the write means when the write count is larger than the second threshold value, the bypass line being shorter than the return line.

5. The sample conveying system according to claim 4, further comprising:

a write count average value calculation mechanism which determines an average value of write counts of the semiconductor memories included in a plurality of sample container holders; and

wherein the write count comparison mechanism includes a control mechanism which permits the writing of information to the semiconductor memory attached to the sample container holder when the write count stored in the semiconductor memory is smaller than a reference value obtained from the average from he write count average valuation calculation mechanism.

6. The sample conveying system according to claim 5, wherein the plurality of threshold values further include a third threshold value, and the sample conveying system further comprises a collecting unit for collecting the sample container holder including the semiconductor memory whose write count is larger than the second threshold value and the third threshold value.

7. The sample conveying system according to claim 1, further comprising a write count changing mechanism for changing the set write count.

8. A sample conveying system comprising:

a conveying line for conveying sample container holders, each of which sample container holders can hold and remove a sample container, to a sample processing unit;

an erase/unload unit for supplying the sample container to the conveying line and for removing the sample containers from the conveying line;

a write means for storing a write count of writing information to each of non-volatile semiconductor memories each of which non-volatile semiconductor memories is attached to one of the sample container holders conveyed from the erase/unload unit;

a write count comparison mechanism for comparing the write count of writing information stored by the write means with a plurality of threshold values including a first threshold value and a second threshold value;

wherein the conveying line control mechanism controls the conveying line to convey the sample container holders through a bypass line into the upper stream of the write means when the write count is larger than the first threshold value and smaller than the second threshold value; and

wherein the conveying line control mechanism controls the conveying line to convey the sample container holders through the return line to the upper stream of the write means when the write count is larger than the second threshold value, the bypass line being shorter than the return line;

a write count average value calculation mechanism which determines an average value of write counts of the semiconductor memories included in a plurality of sample container holders; and

wherein the write count comparison mechanism includes a control mechanism which permits the writing of information to the semiconductor memory attached to the sample container holder when the write count stored in the semiconductor memory is smaller than a reference value obtained from the average from the write count average valuation calculation mechanism;

a return line for returning the sample container holders, which are finished with processes of the sample processing unit, to an upper stream of the write means; and

a conveying line control mechanism for controlling the conveying line and the return line to return each sample container holder including its non-volatile semiconductor memory to skip the writing operation into the semiconductor memories by using the write means and to return the sample container holder into the upper stream of the write means, when the write count comparison mechanism has judged that the write count of the semiconductor memory is larger than the threshold value.

9. The sample conveying system according to claim 8, wherein the plurality of threshold values further include a third threshold value, and the sample conveying system further comprises a collecting unit for collecting the sample container holder including the semiconductor memory whose write count is larger than the second threshold value and the third threshold value.