Digital image processor for a digital camera

• US 8,760,533 B2
• Filed: 05/21/2013
• Issued: 06/24/2014
• Est. Priority Date: 05/29/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Safai, Mohammad A.
• Primary Examiner(s): VU, NGOC YEN T
• Application Number:
  US13/899,256
• Publication Number:
  US 20130250143A1
• Time in Patent Office: 399 Days
• Field of Search: 348/222.1
• US Class Current: 348/222.1
• CPC Class Codes: H04N 2209/046 Colour interpolation to calculate the missing colour values
• CPC Class Codes: H04N 23/617 Upgrading or updating of programs or applications for camera control
• CPC Class Codes: H04N 23/631 Graphical user interfaces [GUI] specially adapted for controlling image capture or setting capture parameters
• CPC Class Codes: H04N 23/843 Demosaicing, e.g. interpolating colour pixel values
• CPC Class Codes: H04N 23/88 for colour balance, e.g. white-balance circuits or colour temperature control
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence
• CPC Class Codes: H04N 9/8047 using transform coding

Abstract

A digital camera is disclosed. In an embodiment, the digital camera has an imaging unit including an image sensor and imaging optics and a digital image processor connected to receive raw digital images from the imaging unit and to process the raw digital images. The digital camera also includes a memory configured to store digital image data that has been processed by the digital image processor and a processor configured to direct retrieval of the digital image data that is stored in the memory and the digital image processor is further configured to generate control signals for use in operation of the imaging unit.

Claims

1. A digital camera, the digital camera comprising:

an imaging unit including an image sensor and imaging optics;

a digital image processor connected to receive raw digital images from the imaging unit and to process the raw digital images;

a memory configured to store digital image data that has been processed by the digital image processor;

a microprocessor that is separate from the digital image processor and configured to direct retrieval of the digital image data that is stored in the memory;

wherein the digital image processor is further configured to generate control signals for use in operation of the imaging unit, wherein the control signals comprise at least one of f-stop control signals, shutter control signals, zoom control signals, and focus control signals;

a control bus that connects the imaging unit directly to the digital image processor and wherein the control signals are provided to the imaging unit from the digital image processor via the control bus.

2. The digital camera of claim 1 wherein the control signals comprise f-stop control signals.

3. The digital camera of claim 1 wherein the control signals comprise shutter control signals.

4. The digital camera of claim 1 wherein the control signals comprise zoom control signals.

5. The digital camera of claim 1 wherein the control signals comprise focus control signals.

6. The digital camera of claim 1 further comprising a programmable universal controller, the programmable universal controller having an f-stop signal generator configured to generate f-stop control signals for use in operation of the imaging unit.

7. The digital camera of claim 1 wherein the digital image processor further comprises a programmable universal controller, the programmable universal controller having a shutter timing signal generator configured to generate shutter timing control signals for use in operation of the imaging unit.

8. The digital camera of claim 1 wherein the digital image processor further comprises a programmable universal controller, the programmable universal controller having a zoom signal generator configured to generate zoom control signals for use in operation of the imaging unit.

9. The digital camera of claim 1 wherein the digital image processor further comprises a programmable universal controller, the programmable universal controller having a focus signal generator configured to generate focus control signals for use in operation of the imaging unit.

10. The digital camera of claim 1 wherein the digital image data that has been processed by the digital image processor is directly stored into the memory without further image processing.

11. A digital camera, the digital camera comprising:

an imaging unit including an image sensor and imaging optics;

a digital image processor connected to receive raw digital images from the imaging unit and to process the raw digital images;

a memory configured to store digital image data that has been processed by the digital image processor;

a microprocessor that is separate from the digital image processor and configured to direct retrieval of the digital image data that is stored in the memory;

wherein the digital image processor is further configured to generate timing signals for use in operation of the imaging unit;

wherein the digital image processor further comprises a programmable universal controller having at least one of;

an f-stop signal generator configured to generate f-stop control signals for use in operation of the imaging unit;

a shutter timing signal generator configured to generate shutter control signals for use in operation of the imaging unit;

a zoom signal generator configured to generate zoom control signals for use in operation of the imaging unit; and

a focus signal generator configured to generate focus control signals for use in operation of the imaging unit;

a control bus that connects the imaging unit directly to the digital image processor and wherein at least one of the f-stop control signals, the shutter control signals, the zoom control signals, and the focus control signals is provided to the imaging unit from the digital image processor via the control bus.

12. The digital camera of claim 11 wherein the timing signals comprise pixel clock signals used to synchronize operation of the image sensor.

13. The digital camera of claim 11 wherein the digital image data that has been processed by the digital image processor is directly stored into the memory without further image processing.

14. A digital camera, the digital camera comprising:

an imaging unit including an image sensor, imaging optics, and a stepper motor for controlling the imaging optics;

a digital image processor connected to receive raw digital images from the imaging unit and to process the raw digital images;

a memory configured to store digital image data that has been processed by the digital image processor;

a microprocessor that is separate from the digital image processor and configured to direct retrieval of the digital image data that is stored in the memory;

wherein the digital image processor is further configured to generate stepper control signals that are provided to the stepper motor of the imaging unit.

15. The digital camera of claim 14 further comprising a control bus that connects the imaging unit to the digital image processor and wherein the stepper control signals are provided to the imaging unit from the digital image processor via the control bus.

16. The digital camera of claim 14 further comprising a control bus that directly connects the imaging unit to the digital image processor and wherein the stepper control signals are provided to the imaging unit from the digital image processor via the control bus.