Techniques for reducing disturbance in a semiconductor memory device
First Claim
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1. A semiconductor memory device comprising:
- a plurality of memory cells; and
data write and sense circuitry coupled to the plurality of memory cells, wherein the data write and sense circuitry is configured to perform a read operation and a writeback operation on a first memory cell of the plurality of memory cells, wherein the data write and sense circuitry is also configured to perform a disturbance recovery operation on a second memory cell of the plurality of memory cells, and wherein the disturbance recovery operation is performed in between the read operation and the writeback operation.
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Abstract
Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.
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22 Claims
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1. A semiconductor memory device comprising:
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a plurality of memory cells; and data write and sense circuitry coupled to the plurality of memory cells, wherein the data write and sense circuitry is configured to perform a read operation and a writeback operation on a first memory cell of the plurality of memory cells, wherein the data write and sense circuitry is also configured to perform a disturbance recovery operation on a second memory cell of the plurality of memory cells, and wherein the disturbance recovery operation is performed in between the read operation and the writeback operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for reducing disturbance in a semiconductor memory device comprising the steps of:
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performing, via data write and sense circuitry, a read operation and a writeback operation on a first memory cell of a plurality of memory cells; and performing, via the data write and sense circuitry, a disturbance recovery operation on a second memory cell of the plurality of memory cells, wherein the disturbance recovery operation is performed in between the read operation and the writeback operation. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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Specification