Multi-rank partial width memory modules

• US 8,760,936 B1
• Filed: 05/20/2013
• Issued: 06/24/2014
• Est. Priority Date: 11/13/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Smith, Michael John
• Primary Examiner(s): Nguyen, Tan
• Application Number:
  US13/898,002
• Time in Patent Office: 400 Days
• Field of Search: 365/189.03, 365/51, 365/52, 365/63, 365/185.11, 365/230.03, 365/230.06
• US Class Current: 365/189.05
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.

Claims

1. An apparatus, comprising:

a memory controller configured to address a first number of ranks of memory, the first number of ranks being greater than one, each rank having a rank width;

a memory bus coupled to the memory controller, the memory bus comprising a data bus and a control bus, the data bus having a number of data signals corresponding to the rank width; and

a plurality of memory modules coupled to the memory controller through the memory bus, wherein a first memory module of the plurality of memory modules comprises;

a plurality of memory circuits grouped into a second number of ranks of memory, the plurality of memory circuits having a first number of data pins; and

one or more buffer circuits connected to the first number of data pins of the plurality of memory circuits, the one or more buffer circuits having a second number of data pins, wherein each of the data pins of the second number of data pins is connected to a different one of the data signals of the memory bus, and wherein the second number of data pins corresponds to a module width that is less than the rank width,

wherein a sum of the module widths of the plurality of memory modules is equal to the rank width.

2. The apparatus of claim 1, wherein the one or more buffer circuits are coupled to the plurality of memory circuits such that a loading of the first number of data pins of the plurality of memory circuits appears to the memory controller as a loading of the second number of data pins of the one or more buffer circuits.

3. The apparatus of claim 1, wherein the second number of ranks of memory is equal to the first number of ranks of memory that the memory controller is configured to address.

4. The apparatus of claim 1, wherein the second number of ranks of memory of each memory module is different from the first number of ranks of memory that the memory controller is configured to address.

5. The apparatus of claim 4, wherein the one or more buffer circuits are configured to transform a data width associated with the memory circuits to the module width.

6. The apparatus of claim 4, wherein the one or more buffer circuits are configured to transform a first data rate associated with the memory circuits to a second, different data rate.

7. The apparatus of claim 1, wherein the plurality of memory modules include two memory modules, and wherein the module width of each of the two memory modules is half of the rank width.

8. The apparatus of claim 1, wherein the plurality of memory modules include three memory modules, and wherein the module width of each of the three memory modules is one third of the rank width.

9. The apparatus of claim 1, wherein the control bus includes a plurality of chip select signals coupled to the memory controller and the plurality of memory modules, and wherein a number of the plurality of chip select signals are equal to the number of ranks of memory that the memory controller is configured to address.

10. The apparatus of claim 9, wherein each memory module further comprises:

a register chip configured to;

receive a chip select signal of the plurality of chip select signals from the memory controller to access a particular rank of memory; and

assert a corresponding chip select signal to memory circuits of the particular rank.

11. An apparatus, comprising:

a memory controller configured to address n ranks of memory, n being a number greater than one, each rank having a rank width of 2×

k;

a memory bus coupled to the memory controller, the memory bus comprising a data bus and a control bus, the data bus having 2×

k data signals that corresponds to the rank width; and

two memory modules coupled to the memory controller through the memory bus, each of the two memory modules comprising;

a plurality of memory circuits grouped into n ranks of memory, the plurality of memory circuits having n×

k data pins; and

one or more buffer circuits connected to the n×

k data pins of the plurality of memory circuits, the one or more buffer circuits having k other data pins each connected to a different one of the 2×

k data signals of the memory bus, wherein the k data pins corresponds to a module width that is less than the rank width,

wherein a sum of the module widths of the two memory modules is equal to the rank width.

12. The apparatus of claim 11, wherein the one or more buffer circuits are coupled to the plurality of memory circuits such that a loading of the n×

k data pins of the plurality of memory circuits appears to the memory controller as a loading of k data pins.

13. The apparatus of claim 11, wherein the control bus includes n chip select signals coupled to the memory controller and the two memory modules.

14. The apparatus of claim 13, wherein each memory module further comprises:

a register chip configured to;

receive a chip select signal of the n select signals from the memory controller to access a particular rank of memory; and

assert a corresponding chip select signal to memory circuits of the particular rank.

15. An apparatus, comprising:

a memory controller configured to address 2×

n ranks of memory, n being a number greater than or equal to one, each rank having a rank width of 2×

k;

a memory bus coupled to the memory controller, the memory bus comprising a data bus and a control bus, the data bus having 2×

k data signals that corresponds to the rank width; and

two memory modules coupled to the memory controller through the memory bus, each of the two memory modules comprising;

a plurality of memory circuits grouped into n ranks of memory, the plurality of memory circuits having 2×

n×

k data pins; and

one or more buffer circuits connected to the 2×

n×

k data pins of the plurality of memory circuits, the one or more buffer circuits having k other data pins each connected to a different one of the 2×

k data signals of the memory bus, wherein the k data pins corresponds to a module width that is less than the rank width,

wherein a sum of the module widths of the two memory modules is equal to the rank width.

16. The apparatus of claim 15, wherein the one or more buffer circuits are coupled to the plurality of memory circuits such that a loading of the 2×

n×

k data pins of the plurality of memory circuits appears to the memory controller as a loading of k data pins.

17. The apparatus of claim 15, wherein the one or more buffer circuits are configured to transform a data width of 2×

k associated with the memory circuits to the module width of k.

18. The apparatus of claim 15, wherein the one or more buffer circuits are configured to transform a first data rate off associated with the memory circuits to a second data rate of 2×

f.

19. The apparatus of claim 15, wherein the control bus includes 2×

n chip select signals coupled to the memory controller and the plurality of memory modules.

20. The apparatus of claim 19, wherein each memory module further comprises:

a register chip configured to;

receive a chip select signal of the 2×

n chip select signals from the memory controller to access a particular rank of memory; and

assert a corresponding chip select signal to memory circuits of the particular rank.