Memory component that samples command/address signals in response to both edges of a clock signal
First Claim
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1. A memory component comprising:
- a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals and a strobe input, each to be coupled to a respective external signaling link;
data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O; and
CA circuitry to sample CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively.
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Abstract
A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component.
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Citations
20 Claims
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1. A memory component comprising:
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a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals and a strobe input, each to be coupled to a respective external signaling link; data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O; and CA circuitry to sample CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of operation within a memory component, the method comprising:
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receiving a first clock signal via a clock input; sampling command/address (CA) signals at an unterminated CA input in response to both rising-edge and falling-edge transitions of the first clock signal, the CA signals indicating read and write operations to be performed within the memory component; in response to CA signals that indicate memory write operations, sampling write data bits received at an on-die terminated data input/output (I/O), the sampling of the write data bits being timed by a strobe signal received via a strobe input; and in response to CA signals that indicate memory read operations, transmitting, via the data I/O, read data bits timed by a second clock signal, each of the read data bits being valid for a respective bit time at the data I/O. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A memory module comprising:
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a circuit board; a termination structure disposed on the circuit board; a command/address (CA) signal path that extends from an edge of the circuit board to the termination structure; and a plurality of memory components disposed on the circuit board and coupled to the CA signal path at respective locations between the edge of the circuit board and the termination structure, each memory component of the plurality of memory components including; a signaling interface having a CA input, a data input/output (I/O), and a strobe input, the CA input being coupled to the CA signal path; data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O; CA circuitry to sample CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively; and an on-die termination coupled to the data I/O. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification