Non-volatile memory and method having a memory array with a high-speed, short bit-line portion

• US 8,760,957 B2
• Filed: 03/27/2012
• Issued: 06/24/2014
• Est. Priority Date: 03/27/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Lee, Seungpil, Park, Jongmin
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/431,670
• Publication Number:
  US 20130258772A1
• Time in Patent Office: 819 Days
• Field of Search: 365/230.03, 365/63, 365/189.08
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions.

Claims

1. A non-volatile memory device, comprising:

an array of memory cells;

rows of word lines and columns of bit lines for accessing said array of memory cells;

said array of memory cells being partitioned along a column direction into a first array portion and a second array portion;

said first array portion having memory cells configured as single-level cells each storing one bit of data;

said second portion having memory cells configured as multi-level cells each storing more than one bit of data;

a set of switches one for each bit line;

said columns of bit lines being partitioned by said set of switches into a first segment of bit lines corresponding to said first array portion and, a second segment of bit lines corresponding to said second array portion;

said first segment of bit lines having first and second ends;

said first ends being coupled adjacent to a set of read/write circuits for reading and writing in parallel a group of memory cells of said array; and

said second ends being switchably connected to said second segment of bit lines via said set of switches for said second segment of bit lines to access said set of read/write circuits via said first segment of bit lines.

2. A non-volatile memory device as in claim 1, further comprising:

a control circuit responsive to operations in said first array portion for switching off said set of switches to eliminate effect of said second segment of bit lines on said first segment of bit lines.

3. A non-volatile memory device as in claim 1, further comprising:

a control circuit responsive to operations in said second array portion for switching on said set of switches to provide coupling of said second segment of bit lines to said set of read/write circuits via said first segment of bit lines.

4. A non-volatile memory device as in claim 1, wherein:

said first segment of bit lines and said second segment of bit lines respectively have lengths in a ratio of less than or equal to 1;

1.

5. A non-volatile memory device as in claim 1, wherein:

said first segment of bit lines and said second segment of bit lines respectively have RC constants in a ratio of less than or equal to 1;

4.

6. A non-volatile memory device as in claim 1, wherein:

said first array portion acts as a cache storage of data received from a host.

7. A non-volatile memory device as in claim 6, wherein:

data cached in said first array portion is eventually transferred to said second array portion.

8. A non-volatile memory device as in claim 1, wherein:

said array of memory cells is of the NAND type.

9. A method of operating, a non-volatile memory device having an array of memory cells, comprising:

accessing said array of memory cells with rows of word lines and columns of bit lines;

partitioning said array of memory cells along a column direction into a first array portion and a second array portion, said first array portion being adjacent a set of read/write circuit;

configuring memory cells of said first array portion to operate as single-level cells each storing one bit of data;

configuring memory cells of said second portion to operate as multi-level cells each storing more than one bit of data;

providing a set of switches, one for each bit line;

partitioning said columns of bit lines by said set of switches into a first segment of bit lines corresponding to said first array portion and a second segment of bit lines corresponding to said second array portion;

said first segment of bit lines having first ends adjacent the set of read/write circuits and second ends adjacent the second segment of bit lines;

coupling first ends of said first segment of bit lines to the set of read/write circuits;

switching off the set of switches to isolate the first segment of bit lines from the second segment of bit lines when reading and writing in parallel a group of memory cells of the first array portion; and

switching on the set of switches to connect the first segment of bit lines to the second segment of bit lines when reading and writing in parallel a group of memory cells of the second array portion.

10. The method as in claim 9, further comprising:

responsive to operations in said first array portion, decoupling said second segment of bit lines from said second ends of said first segment of bit lines to eliminate effect of said second segment of bit lines on said first segment of bit lines.

11. The method as in claim 9, further comprising:

responsive to operations in said second array portion, coupling said second segment of bit lines to said second ends of said first segment of bit lines to access said set of read/write circuits.

12. The method as in claim 9, wherein:

said first segment of bit lines and said second segment of bit lines respectively have lengths in a ratio of less than or equal to 1;

1.

13. The method as in claim 9, wherein:

said first segment of bit lines and said second segment of bit lines respectively have RC constants in a ratio of less than or equal to 1;

4.

14. The method as in claim 9, wherein:

said first array portion acts as a cache storage of data received from a host.

15. The method as in claim 14, wherein:

data cached in said first array portion is eventually transferred to said second array portion.

16. The method as in claim 9, wherein:

said array of memory cells is of the NAND type.