Memory device and electronic device

• US 8,760,959 B2
• Filed: 03/13/2012
• Issued: 06/24/2014
• Est. Priority Date: 03/18/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsubayashi, Daisuke
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/418,546
• Publication Number:
  US 20120236634A1
• Time in Patent Office: 833 Days
• Field of Search: 365/230.06, 365/189.15, 365/104, 365/189.04, 365/189.16, 365/210.12, 365/220, 365/221
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

Claims

1. A memory device comprising:

a first memory cell;

a second memory cell provided in a same row as the first memory cell;

a row selection line;

a first column selection line; and

a second column selection line,

wherein the first memory cell includes a field-effect transistor comprising a first gate and a second gate and controlling at least data writing and data holding in the first memory cell by being turned on or off,

wherein the second memory cell includes a field-effect transistor comprising a first gate and a second gate and controlling at least data writing and data holding in the second memory cell by being turned on or off,

wherein the row selection line is electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell,

wherein the first column selection line is electrically connected to the second gate of the field-effect transistor included in the first memory cell, and

wherein the second column selection line is electrically connected to the second gate of the field-effect transistor included in the second memory cell.

2. The memory device according to claim 1, wherein the field-effect transistor in the first or second memory cell includes an oxide semiconductor layer in which a channel is formed.

6. An electronic device comprising the memory device according to claim 1.

3. A memory device comprising:

a first memory cell;

a second memory cell provided in a same row as the first memory cell;

a first data line;

a second data line;

a row selection line;

a first column selection line;

a second column selection line; and

a reading selection line,

wherein the first memory cell and the second memory cell each comprise;

a first field-effect transistor including a first source, a first drain, a first gate, and a second gate; and

a second field-effect transistor including a second source, a second drain, a third gate, and a fourth gate,

wherein a data signal is input to one of the first source and the first drain,

wherein the third gate is electrically connected to one of the second source and the second drain, and

wherein the fourth gate is electrically connected the other of the first source and the first drain of the first field-effect transistor,

wherein the first data line is electrically connected to the one of the first source and the first drain of the first field-effect transistor included in the first memory cell,

wherein the second data line is electrically connected to the one of the first source and the first drain of the first field-effect transistor included in the second memory cell and the one of the second source and the second drain of the second field-effect transistor included in the second memory cell,

wherein the row selection line is electrically connected to the first gates of the first field-effect transistors included in the first memory cell and the second memory cell,

wherein the first column selection line is electrically connected to the second gate of the first field-effect transistor included in the first memory cell,

wherein the second column selection line is electrically connected to the second gate of the first field-effect transistor included in the second memory cell, and

wherein the reading selection line is electrically connected to the other of the second source and the second drain of the second field-effect transistor included in the first memory cell and the other of the second source and the second drain of the second field-effect transistor included in the second memory cell.

4. The memory device according to claim 3, wherein the first field-effect transistor includes an oxide semiconductor layer in which a channel is formed.

5. The memory device according to claim 4, wherein the second field-effect transistor is stacked over the first field-effect transistor.

7. An electronic device comprising the memory device according to claim 3.