Matrix operations in an integrated circuit device

• US 8,762,443 B1
• Filed: 11/15/2011
• Issued: 06/24/2014
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Kurtz, Brian L.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US13/296,360
• Time in Patent Office: 952 Days
• Field of Search: 708/520, 708/514, 708/607
• US Class Current: 708/520
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

Matrix operations circuitry for performing operations on submatrices of an input matrix includes a first working memory in which individual ones of the submatrices are operated on. The first working memory has a first submatrix size. The matrix operations circuitry also includes a second working memory in which a collection of the submatrices, that have been operated on in the first working memory, is operated on. The second working memory has an optimum burst size, and the first submatrix size is matched to the optimum burst size.

Claims

1. Matrix operations circuitry for performing operations on submatrices of an input matrix, said matrix operations circuitry comprising:

a first working memory in which individual ones of said submatrices are operated on, said first working memory having a first submatrix size; and

a second working memory in which a collection of said submatrices, that have been operated on in said first working memory, is operated on, said second working memory having an optimum burst size;

wherein;

said first submatrix size is matched to said optimum burst size.

2. The matrix operations circuitry of claim 1 wherein said first submatrix size is equal to said optimum burst size.

3. The matrix operations circuitry of claim 1 wherein said input matrix has dimensions, at least one of said dimensions being other than a prime number.

4. The matrix operations circuitry of claim 1 wherein said operations comprise transposing said input matrix, said matrix operations circuitry further comprising:

first address generation circuitry for selection of one of said submatrices from said input matrix for reading into said first working memory, and for controlling transposition of said one of said submatrices in said first working memory.

5. The matrix operations circuitry of claim 4 further comprising second address generation circuitry for controlling transposition of positions of said submatrices within said input matrix in said second working memory.

6. The matrix operations circuitry of claim 5 wherein:

said first working memory is part of an integrated circuit device; and

said second working memory is external to said integrated circuit device;

said matrix operations circuitry further comprising;

an external memory interface on said integrated circuit device, said external memory interface being coupled to said first working memory, said second working memory, and said second address generation circuitry, and reading and writing data to and from said second working memory under control of said second address generation circuitry.

7. The matrix operations circuitry of claim 6 further comprising input matrix storage external to said integrated circuit device and coupled to said first working memory and to said first address generation circuitry.

8. The matrix operations circuitry of claim 6 wherein said integrated circuit device is programmable.

9. The matrix operations circuitry of claim 8 wherein said programmable integrated circuit device is a programmable logic device.

10. A method of configuring a programmable integrated circuit device as matrix operations circuitry for performing operations on submatrices of an input matrix, said method comprising:

configuring memory of said programmable integrated circuit device as a first working memory in which individual ones of said submatrices are operated on, said first working memory having a first submatrix size; and

configuring a second working memory in which a collection of said submatrices, that have been operated on in said first working memory, is operated on, said second working memory having an optimum burst size;

wherein;

said first submatrix size is configured to be matched to said optimum burst size.

11. The method of claim 10 wherein said first submatrix size is configured to be equal to said optimum burst size.

12. The method of claim 10 wherein said input matrix has dimensions, at least one of said dimensions being other than a prime number.

13. The method of claim 10 wherein said operations comprise transposing said input matrix, said method further comprising:

configuring logic of said programmable integrated circuit device as first address generation circuitry for selection of one of said submatrices from said input matrix for reading into said first working memory, and for controlling transposition of said one of said submatrices in said first working memory.

14. The method of claim 13 further comprising configuring logic of said programmable integrated circuit device as second address generation circuitry for controlling transposition of positions of said submatrices within said input matrix in said second working memory.

15. The method of claim 14 wherein:

said second working memory is external to said programmable integrated circuit device;

said method further comprising;

configuring logic of said programmable integrated circuit device as an external memory interface that (a) is coupled to said first working memory, said second working memory, and said second address generation circuitry, and (b) reads and writes data to and from said second working memory under control of said second address generation circuitry.

16. The method of claim 15 wherein:

said input matrix is stored in input storage external to said integrated circuit device; and

said configuring logic of said programmable integrated circuit device as said first address generation circuitry comprises configuring said first address generation circuitry to be coupled to said first working memory and to said first address generation circuitry.

17. The method of claim 15 wherein said programmable integrated circuit device is a programmable logic device.

18. A non-transitory machine-readable data storage medium encoded with machine-executable instructions for configuring a programmable integrated circuit device as matrix operations circuitry for performing operations on submatrices of an input matrix, said instructions comprising:

instructions to configure memory of said programmable integrated circuit device as a first working memory in which individual ones of said submatrices are operated on, said first working memory having a first submatrix size; and

instructions to configure a second working memory in which a collection of said submatrices, that have been operated on in said first working memory, is operated on, said second working memory having an optimum burst size;

wherein;

in said instructions to configure memory of said programmable integrated circuit device as a first working memory, said first submatirx size is configured to be matched to said optimum burst size.

19. The non-transitory machine-readable data storage medium of claim 18 wherein in instructions to configure memory of said programmable integrated circuit device as a first working memory, said first submatrix size is configured to be equal to said optimum burst size.

20. The non-transitory machine-readable data storage medium of claim 18 wherein said operations comprise transposing said input matrix, said instructions further comprising:

instructions to configure logic of said programmable integrated circuit device as first address generation circuitry for selection of one of said submatrices from said input matrix for reading into said first working memory, and for controlling transposition of said one of said submatrices in said first working memory.

21. The non-transitory machine-readable data storage medium of claim 20 wherein said instructions further comprise instructions to configure logic of said programmable integrated circuit device as second address generation circuitry for controlling transposition of positions of said submatrices within said input matrix in said second working memory.

22. The non-transitory machine-readable data storage medium of claim 21 wherein:

said instructions to configure said second working memory comprise instructions to configure memory external to said programmable integrated circuit device as said second working memory;

said instructions further comprising;

instructions to configure logic of said programmable integrated circuit device as an external memory interface that (a) is coupled to said first working memory, said second working memory, and said second address generation circuitry, and (b) reads and writes data to and from said second working memory under control of said second address generation circuitry.