Delegating a poll operation to another device

• US 8,762,599 B2
• Filed: 12/28/2012
• Issued: 06/24/2014
• Est. Priority Date: 06/11/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Espig, Michael J., Fang, Zhen, Iyer, Ravishankar, Harriman, David J.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Shyu, Jing-Yih
• Application Number:
  US13/729,172
• Publication Number:
  US 20130138843A1
• Time in Patent Office: 543 Days
• Field of Search: None
• US Class Current: 710/46
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a core to generate a registration message to delegate a poll operation to an input/output (IO) interconnect;

the IO interconnect coupled to the core, the IO interconnect to include a poll table having a plurality of entries each having a first address field to store a first address to be received in a registration message, a destination address field to store a destination address in a system memory to be received in the registration message, and an initial value field to store an initial value associated with the first address received in the registration message; and

at least one device coupled to the IO interconnect to perform an operation for an application to be executed on the core and to include at least one status register, the IO interconnect including a poll delegation logic to poll the at least one status register responsive to information in a poll table entry, and to issue a write transaction to the destination address if a polled value of the at least one status register differs from an initial value of the at least one status register stored in the poll table entry.

2. The apparatus of claim 1, wherein the poll delegation logic is to issue a read request to the at least one device at a predetermined interval to perform the poll.

3. The apparatus of claim 1, wherein the poll delegation logic is to perform a comparison between data received from the at least one device responsive to a read request and the initial value and to issue the write transaction when the data and the initial value differ.

4. The apparatus of claim 1, wherein the at least one device is to update the initial value to the polled value upon completion of the operation.

5. The apparatus of claim 1, wherein the apparatus comprises a system on a chip (SoC) formed on a single semiconductor die, and the at least one device comprises an intellectual property (IP) block.

6. The apparatus of claim 1, wherein the core is to send an eviction message to the IO interconnect to delete an entry in the poll table when an application corresponding to the entry is terminated.

7. The apparatus of claim 1, wherein the core is to execute a first instruction to set up the destination address and a second instruction to cause the core to enter a low power state until the destination address is updated.

8. The apparatus of claim 7, wherein the core is to send the registration message to the IO interconnect prior to execution of the first and second instructions.

9. A system comprising:

a system on a chip (SoC) including;

at least one core including a first logic to execute a first instruction to set up a monitored address in a memory, a second logic to cause the at least one core to enter a low power state when a predetermined instruction follows the first instruction, and a third logic to monitor for a write to the monitored address;

a first input/output (TO) interconnect to include a poll table to store a tuple including an identifier of a register in an intellectual property (IP) block coupled to the first IO interconnect, the monitored address in the memory, and an initial value associated with the register, and a delegation logic to receive a delegation message from the at least one core, and based on the tuple, obtain a current value of the register and responsive to a difference between the current value and the initial value, issue a coherent write operation to write data corresponding to the current value to the monitored address in the memory via a message signaling interrupt; and

the IP block coupled to the first IO interconnect to include the register and to perform a function for an application to execute on the at least one core; and

the memory coupled to the SoC via a memory interconnect, wherein the third logic is to cause the at least one core to exit the low power state responsive to the data being written to the monitored address.

10. The system of claim 9, wherein the at least one core is to continue execution of the application at a next instruction following the predetermined instruction after the exit from the low power state.

11. The system of claim 10, wherein the IP block is to update the initial value to the current value upon completion of the function.

12. The system of claim 10, wherein the at least one core is to send the delegation message to the first IO interconnect with the tuple prior to execution of the first instruction.

13. A method comprising:

receiving a registration message from a host processor in an interconnect coupled between the host processor and a device, the registration message to delegate a poll operation with respect to the device to the interconnect;

storing information regarding a device monitored location, a memory monitored address, and an initial value of the device monitored location in a poll table associated with the interconnect;

sending, via a poll delegation logic of the interconnect, a read request to the device to poll the device, comparing the initial value with a device value obtained from the device monitored location, and reporting a result of the poll to the host processor if the device value is different than the initial value;

issuing a write request from the interconnect to the memory monitored address in a system memory to report the result;

issuing a message signaling interrupt from the interconnect to the system memory to issue the write request; and

wherein the host processor is placed into a low power state after sending the registration message, and responsive to the write to the memory monitored address, the host processor is to exit the low power state.

14. The method of claim 13, wherein the poll table includes a plurality of entries each including a device monitored location, a memory monitored address, and an initial value, and further comprising sending a read request to the device for each of the plurality of entries.

15. The method of claim 13, wherein the device monitored location corresponds to a status register of the device, and associating the status register with the memory monitored address via the poll table.

16. The method of claim 13, further comprising initiating the registration message via an application, and performing a first function on the device for the application, wherein the application is to initiate the first function after the information is stored in the poll table, and to cause the host processor to enter into a low power state.