Low-power audio decoding and playback using cached images

• US 8,762,644 B2
• Filed: 02/25/2011
• Issued: 06/24/2014
• Est. Priority Date: 10/15/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Castelloe, Michael Warren
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): BERNARD, DANIEL J
• Application Number:
  US13/034,910
• Publication Number:
  US 20120096223A1
• Time in Patent Office: 1,215 Days
• Field of Search: None
• US Class Current: 711/118
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A particular method includes loading one or more memory images into a multi-way cache. The memory images are associated with an audio decoder, and the multi-way cache is accessible to a processor. Each of the memory images is sized not to exceed a page size of the multi-way cache.

Claims

1. A method comprising:

allocating one or more memory regions of a memory that is accessible to a processor, wherein the one or more memory regions are each allocated to a particular memory image of one or more memory images associated with a first audio decoder;

loading the one or more memory images to a multi-way cache;

decoding a first audio stream at the first audio decoder and a second audio stream at a second audio decoder;

terminating the decoding of the second audio stream at the second audio decoder; and

decoding the first audio stream at the first audio decoder after terminating the decoding of the second audio stream.

2. The method of claim 1, wherein a size of each of the one or more memory images is equal to a page size of the multi-way cache.

3. The method of claim 1, wherein the first audio decoder is operable to decode one or more audio streams.

4. The method of claim 1, further comprising detecting a termination of the second audio stream.

5. The method of claim 1, wherein the one or more memory images includes three or more memory images, wherein a first memory image of the one or more memory images includes audio decoder program instructions, wherein a second memory image of the one or more memory images corresponds to a dynamic memory allocation region, and wherein a third memory image of the one or more memory images includes post-processing program instructions.

6. The method of claim 1, wherein the one or more memory images are loaded to the multi-way cache independently of intervention from an application processor.

7. The method of claim 1, further comprising accessing, at a third memory integrated with the processor, program instructions that are common to multiple audio decoders.

8. The method of claim 1, wherein the processor comprises a digital signal processor.

9. The method of claim 1, wherein a first memory image of the one or more memory images is configured to be used for audio decoding in a low power mode of the processor and in a non-low power mode of the processor.

10. The method of claim 1, wherein the memory is a random access memory.

11. The method of claim 1, further comprising decoding the first audio stream at the first audio decoder without the first audio decoder causing a cache miss to occur at the multi-way cache.

12. The method of claim 11, further comprising decoding a third audio stream at a third audio decoder without the third audio decoder causing cache misses to occur at the multi-way cache.

13. The method of claim 1, further comprising:

receiving audio data;

wherein the one or more memory images are loaded in response to determining that the audio data corresponds to the first audio decoder;

decoding the audio data at the first audio decoder without causing a cache miss to occur at the multi-way cache; and

providing processed audio data to an output port of the processor.

14. The method of claim 13, further comprising:

applying one or more post-processing functions to decoded audio data to generate post-processed audio data, wherein the one or more post-processing functions are specific to the first audio decoder; and

applying one or more common processing functions to the post-processed audio data to generate the processed audio data, wherein the one or more common processing functions are common to a plurality of audio decoders.

15. The method of claim 1, wherein a size of each of the one or more regions of memory is less than or equal to a page size of the multi-way cache, and wherein loading the one or more memory images to the multi-way cache enables audio decoding without the first audio decoder causing cache misses to occur at the multi-way cache.

16. The method of claim 15, wherein the audio decoding is performed after loading the one or more memory images to the multi-way cache without accessing a higher-level memory that is available to the processor, and wherein the first audio stream and the second audio stream are decoded concurrently.

17. The method of claim 1, further comprising initiating a process to cause loading of an entire memory image of the one or more memory images into the multi-way cache.

18. The method of claim 17, wherein the process comprises a background thread of the processor.

19. The method of claim 17, wherein the process is initiated in response to detecting a start or a stop of an audio decoding process.

20. The method of claim 1, further comprising applying one or more post-processing functions to decoded audio data to generate post-processed audio data, wherein the one or more post-processing functions are specific to the first audio decoder.

21. The method of claim 20, further comprising applying one or more common processing operations to the post-processed audio data to generate processed audio data, wherein the one or more common processing operations are common to some of the audio decoders.

22. The method of claim 1, wherein the one or more memory images are loaded to the multi-way cache without an audible interruption in the first audio stream or in the second audio stream.

23. The method of claim 1, further comprising:

decoding the first audio stream at the first audio decoder without the first audio decoder causing a cache miss to occur at the multi-way cache;

detecting a termination of the first audio stream and an initiation of a third audio stream to be decoded by a third audio decoder;

loading one or more memory images associated with the third audio decoder to the multi-way cache; and

decoding the third audio stream at the third audio decoder without the third audio decoder causing cache misses to occur at the multi-way cache.

24. The method of claim 23, wherein the one or more memory images associated with the third audio decoder are loaded to the multi-way cache without an audible interruption in the first audio stream or in the third audio stream.

25. The method of claim 23, wherein the one or more memory images associated with the third audio decoder are loaded to the multi-way cache independently of intervention from an application processor.

26. The method of claim 1, wherein the one or more memory images are each loaded from the memory to the multi-way cache and wherein the one or more memory images are each aligned in the memory to be loaded into a corresponding single page of the multi-way cache.

27. The method of claim 26, wherein the one or more memory images in the memory are accessible to enable audio decoding and low-power audio decoding when all of the one or more memory images are loaded into the multi-way cache.

28. The method of claim 26, wherein the memory includes one or more memory images associated with the second audio decoder.

29. The method of claim 26, wherein the memory includes at least one memory image that is common to a plurality of audio decoders.

30. The method of claim 26, wherein the memory includes a dynamic memory allocation region.

31. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:

allocate one or more memory regions of a memory that is accessible to the processor, wherein the one or more memory regions are each allocated to a particular memory image of one or more memory images associated with a first audio decoder;

load the one or more memory images to a multi-way cache;

decode a first audio stream at the first audio decoder and a second audio stream at a second audio decoder;

terminate the decoding of the second audio stream at the second audio decoder; and

decode the first audio stream at the first audio decoder after terminating the decoding of the second audio stream.

32. The non-transitory computer-readable storage medium of claim 31, wherein loading the one or more memory images to the multi-way cache enables audio decoding without the first audio decoder causing any cache misses to occur at the multi-way cache.

33. The non-transitory computer-readable storage medium of claim 31, wherein a size of each of the one or more memory images is equal to a page size of the multi-way cache.

34. The non-transitory computer-readable storage medium of claim 31, wherein a size of each of the one or more regions of memory is less than or equal to a page size of the multi-way cache.

35. An electronic device, comprising:

a processor; and

a multi-way cache accessible to the processor,

wherein the processor is configured to;

allocate one or more memory regions of a memory, wherein the one or more memory regions are each allocated to a particular memory image of one or more memory images associated with a first audio decoder;

load the one or more memory images associated with an audio decoder into the multi-way cache;

terminate the decoding of the second audio stream at the second audio decoder; and

decode the first audio stream at the first audio decoder after terminating the decoding of the second audio stream.

36. The electronic device of claim 35, wherein a size of each of the one or more regions of memory is less than or equal to a page size of the multi-way cache.

37. The electronic device of claim 35, further comprising common processing circuitry configured to apply one or more common processing operations to post-processed audio data to generate processed audio data, wherein the one or more common processing operations are common to a plurality of audio decoders.

38. The electronic device of claim 35, wherein loading the one or more memory images into the multi-way cache enables audio decoding without the first audio decoder causing cache misses to occur at the multi-way cache.

39. The electronic device of claim 35, wherein the memory is a random access memory and further comprising:

a low-power memory accessible to the processor;

an application processor configured to cause audio data to be retrieved from the random access memory and stored at the low-power memory, wherein the audio decoder is configured to decode audio data retrieved from the low-power memory to generate decoded audio data;

post-processing circuitry configured to apply one or more post-processing operations to the decoded audio data to generate post-processed audio data, wherein the one or more post-processing operations are specific to the audio decoder; and

common processing circuitry configured to apply one or more common processing operations to the post-processed audio data to generate the processed audio data, wherein the one or more common processing operations are common to a plurality of audio decoders; and

an output port configured to output the processed audio data.

40. An apparatus, comprising:

means for processing data; and

means for caching data in a plurality of cache ways,

wherein the means for caching data is accessible to the means for processing data, and

wherein the means for processing data is configured to;

allocate one or more memory regions of means for storing data, wherein the one or more memory regions are each allocated to a particular memory image of one or more memory images associated with first means for decoding audio data;

load the one or more memory images associated with an audio decoder into the means for caching data;

decode a first audio stream at the first means for decoding audio data and a second audio stream at a second means for decoding audio data;

terminate the decoding of the second audio stream at the second means for decoding audio data; and

decode the first audio stream at the first means for decoding audio data after terminating the decoding of the second audio stream.

41. The apparatus of claim 40, wherein loading the one or more memory images to the means for caching data enables audio decoding without the means for decoding audio data causing cache misses to occur at the means for caching data.

42. The apparatus of claim 40, wherein a size of each of the one or more memory images is equal to a page size of the means for caching data.

43. The apparatus of claim 40, wherein the means for decoding audio data is an Advanced Audio Coding (AAC)-type audio decoder, a Moving Picture Experts Group Audio Layer III (MP3)-type audio decoder, a speech audio decoder, a pulse-code modulation (PCM) audio decoder, or any combination thereof.

44. The apparatus of claim 40, further comprising means for applying one or more post-processing operations to decoded audio data to generate post-processed audio data, wherein the one or more post-processing operations are specific to the first audio decoder.