Systems and methods for handling immediate data errors in flash memory

• US 8,762,800 B1
• Filed: 01/28/2013
• Issued: 06/24/2014
• Est. Priority Date: 01/31/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: Weingarten, Hanan, Levy, Shmuel
• Primary Examiner(s): Lottich, Joshua P
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US13/751,580
• Time in Patent Office: 512 Days
• Field of Search: 714/758, 714/54, 714/746, 714/6, 711/103
• US Class Current: 714/718
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3463 Circuits or methods to detect overprogrammed nonvolatile memory cells, usually during program verification
• CPC Class Codes: G11C 16/3486 Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A system that includes a multiplicity of flash memory cells; a reading apparatus; a writing apparatus for writing logical data from temporary memory into individual flash memory cells from among said multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to said reading apparatus, at least one bit-worth of said logical data; and a special cell marking apparatus operative to store an earmark in at least an individual one of said multiplicity of flash memory cells for subsequent special treatment.

Claims

1. A system comprising:

a multiplicity of flash memory cells;

a reading apparatus;

a writing apparatus for writing logical data from temporary memory into individual flash memory cells from among said multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to said reading apparatus, at least one bit-worth of said logical data; and

a special cell marking apparatus operative to store an earmark in a certain flash memory cell of said multiplicity of flash memory cells for subsequent special-treatment by programming the certain flash memory cell to store a dummy physical level, said dummy physical level differs from any physical level used for representing one or more logical data bits in the certain flash memory cell.

2. The system according to claim 1 wherein each one of the multiplicity of flash memory is programmable to a plurality (2 by the power of n) of physical levels that represent logical values of n logical data bits and to the dummy physical level, n being a positive integer.

3. The system according to claim 1 wherein the dummy physical level is an erasure physical value.

4. The system according to claim 1 wherein the subsequent special treatment comprises error correction.

5. The system according to claim 1 comprising a reading circuitry that is arranged to read a content of the certain flash memory cell to provide a dummy value;

and a microcontroller that is arranged to detect the dummy value, apply an error correction process to provide a correct value and to replace the dummy value with the correct value.

6. The system according to claim 1 wherein the special cell marking apparatus is operative to store an earmark in each one of a plurality of flash memory cells of said multiplicity of flash memory cells for subsequent special-treatment by programming each one of the plurality of flash memory cell to store the dummy physical level.

7. A flash memory utilization method comprising:

writing logical data from temporary memory into individual flash memory cells from among a multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to reading apparatus, at least one bit-worth of said logical data; and

earmarking, by a special cell marking apparatus, a certain flash memory cell of said multiplicity of flash memory cells for subsequent special treatment by programming the certain flash memory cells to store a dummy physical, said dummy physical level differs from any physical level used for representing one or more logical data bits in the certain flash memory cell.

8. The method according to claim 7 wherein each one of the multiplicity of flash memory is programmable to a plurality (2 by the power of n) of physical levels that represent logical values of n logical data bits and to the dummy physical level, n being a positive integer.

9. The method according to claim 7 wherein the dummy physical level is an erasure physical value.

10. The method according to claim 7 wherein the subsequent special treatment comprises error correction.

11. The method according to claim 7 comprising reading a flash memory cell that is programmed to store the dummy physical level to provide a dummy value;

detecting the dummy value, applying an error correction process to provide a correct value and replacing the dummy value with the correct value.

12. The method according to claim 7 comprising storing an earmark in each one of a plurality of flash memory cells of said multiplicity of flash memory cells for subsequent special-treatment by programming each one of the plurality of flash memory cell to store the dummy physical level.

13. A flash memory utilization method comprising:

writing first logical data from temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors;

reading said physical representation from the cells, thereby to generate, and store in said temporary memory, second logical data which if read immediately is identical to said first logical data other than said known errors; and

controlling, by a controlling apparatus, said writing apparatus and said reading apparatus, wherein the controlling comprises;

identifying said known errors by comparing said first logical data to second logical data read immediately after said physical representation is generated, storing information characterizing said known errors;

wherein said information enables addresses of said known errors to be reconstructed when said second logical data is next read;

wherein said information comprises a total number of known errors to be identified by the controlling apparatus and a serial number of a set comprising the addresses of the known errors, within a sequence out of multiple sequences, the sequence having a predetermined order of all possible sets of the addresses of the known errors given the total number of known errors;

wherein different sequences of the multiple sequences are associated with different numbers of known addresses; and

using said information, when said second logical data is next read, to correct said known errors.

14. A non-transitory machine readable memory that stores instructions for:

writing logical data from temporary memory into individual flash memory cells from among a multiplicity of flash memory cells, thereby to generate a physical representation of the logical data including a plurality of physical levels at least some of which represent, to reading apparatus, at least one bit-worth of said logical data; and

earmarking a certain flash memory cell of said multiplicity of flash memory cells for subsequent treatment by programming the certain flash memory cells to store a dummy physical level, said dummy physical level differs from any physical level used for representing one or more logical data bits in the certain flash memory cells.

15. The non-transitory machine readable memory according to claim 14 wherein each one of the multiplicity of flash memory is programmable to a plurality (2 by the power of n) of physical levels that represent logical values of n logical data bits and to the dummy physical level, n being a positive integer.

16. The non-transitory machine readable memory according to claim 14 wherein the dummy physical level is an erasure physical value.

17. The non-transitory machine readable memory according to claim 14 wherein the subsequent special treatment comprises error correction.

18. The non-transitory machine readable memory according to claim 14 that stores instructions for reading a flash memory cell that is programmed to store the dummy physical level to provide a dummy value;

detecting the dummy value, applying an error correction process to provide a correct value and replacing the dummy value with the correct value.

19. The non-transitory machine readable memory according to claim 14 that stores instructions for storing an earmark in each one of a plurality of flash memory cells of said multiplicity of flash memory cells for subsequent special-treatment by programming each one of the plurality of flash memory cell to store the dummy physical level.

20. A non-transitory machine readable memory that stores instructions for:

writing first logical data from temporary memory into flash memory cells having at least two levels, thereby to generate a physical representation of the first logical data including known errors;

reading said physical representation from the cells, thereby to generate, and store in said temporary memory, second logical data which if read immediately is identical to said first logical data other than said known errors; and

controlling said writing apparatus and said reading apparatus, wherein the controlling comprises;

identifying said known errors by comparing said first logical data to second logical data read immediately after said physical representation is generated, storing information characterizing said known errors;

wherein said information enables addresses of said known errors to be reconstructed when said second logical data is next read;

wherein said information comprises a total number of known errors to be identified by a controlling apparatus and a serial number of a set comprising the addresses of the known errors, within a sequence out of multiple sequences, the sequence having a predetermined order of all possible sets of the addresses of the known errors given the total number of known errors;

wherein different sequences of the multiple sequences are associated with different numbers of known addresses; and

using said information, when said second logical data is next read, to correct said known errors.